diff -urN openimpact-1.0rc4/autom4te.cache/output.0 openimpact-1.0rc4.Limpact/autom4te.cache/output.0
--- openimpact-1.0rc4/autom4te.cache/output.0	2007-02-07 15:19:58.869096527 -0600
+++ openimpact-1.0rc4.Limpact/autom4te.cache/output.0	2007-02-07 15:22:32.108970940 -0600
@@ -1,6 +1,6 @@
 @%:@! /bin/sh
 @%:@ Guess values for system-dependent variables and create Makefiles.
-@%:@ Generated by GNU Autoconf 2.54 for openimpact 1.0rc4.
+@%:@ Generated by GNU Autoconf 2.54 for openimpact 1.0rc4.Limpact.
 @%:@
 @%:@ Report bugs to <rkidd@crhc.uiuc.edu>.
 @%:@ 
@@ -265,8 +265,8 @@
 # Identity of this package.
 PACKAGE_NAME='openimpact'
 PACKAGE_TARNAME='openimpact'
-PACKAGE_VERSION='1.0rc4'
-PACKAGE_STRING='openimpact 1.0rc4'
+PACKAGE_VERSION='1.0rc4.Limpact'
+PACKAGE_STRING='openimpact 1.0rc4.Limpact'
 PACKAGE_BUGREPORT='rkidd@crhc.uiuc.edu'
 
 ac_unique_file="src/Lcode/Lcode/l_code.c"
@@ -776,7 +776,7 @@
   # Omit some internal or obsolete options to make the list less imposing.
   # This message is too long to be a string in the A/UX 3.1 sh.
   cat <<_ACEOF
-\`configure' configures openimpact 1.0rc4 to adapt to many kinds of systems.
+\`configure' configures openimpact 1.0rc4.Limpact to adapt to many kinds of systems.
 
 Usage: $0 [OPTION]... [VAR=VALUE]...
 
@@ -843,7 +843,7 @@
 
 if test -n "$ac_init_help"; then
   case $ac_init_help in
-     short | recursive ) echo "Configuration of openimpact 1.0rc4:";;
+     short | recursive ) echo "Configuration of openimpact 1.0rc4.Limpact:";;
    esac
   cat <<\_ACEOF
 
@@ -936,7 +936,7 @@
 test -n "$ac_init_help" && exit 0
 if $ac_init_version; then
   cat <<\_ACEOF
-openimpact configure 1.0rc4
+openimpact configure 1.0rc4.Limpact
 generated by GNU Autoconf 2.54
 
 Copyright 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002
@@ -951,7 +951,7 @@
 This file contains any messages produced by compilers while
 running configure, to aid debugging if configure makes a mistake.
 
-It was created by openimpact $as_me 1.0rc4, which was
+It was created by openimpact $as_me 1.0rc4.Limpact, which was
 generated by GNU Autoconf 2.54.  Invocation command line was
 
   $ $0 $@
@@ -1603,7 +1603,7 @@
 
 # Define the identity of the package.
  PACKAGE=openimpact
- VERSION=1.0rc4
+ VERSION=1.0rc4.Limpact
 
 
 cat >>confdefs.h <<_ACEOF
@@ -12812,7 +12812,7 @@
 } >&5
 cat >&5 <<_CSEOF
 
-This file was extended by openimpact $as_me 1.0rc4, which was
+This file was extended by openimpact $as_me 1.0rc4.Limpact, which was
 generated by GNU Autoconf 2.54.  Invocation command line was
 
   CONFIG_FILES    = $CONFIG_FILES
@@ -12874,7 +12874,7 @@
 
 cat >>$CONFIG_STATUS <<_ACEOF
 ac_cs_version="\\
-openimpact config.status 1.0rc4
+openimpact config.status 1.0rc4.Limpact
 configured by $0, generated by GNU Autoconf 2.54,
   with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\"
 
diff -urN openimpact-1.0rc4/autom4te.cache/traces.0 openimpact-1.0rc4.Limpact/autom4te.cache/traces.0
--- openimpact-1.0rc4/autom4te.cache/traces.0	2007-02-07 15:19:58.869096527 -0600
+++ openimpact-1.0rc4.Limpact/autom4te.cache/traces.0	2007-02-07 15:22:32.108970940 -0600
@@ -1,5 +1,5 @@
 m4trace:aclocal.m4:50: -1- m4_pattern_allow([^AM_[A-Z]+FLAGS$])
-m4trace:configure.ac:50: -1- AC_INIT([openimpact], [1.0rc4], [rkidd@crhc.uiuc.edu])
+m4trace:configure.ac:50: -1- AC_INIT([openimpact], [1.0rc4.Limpact], [rkidd@crhc.uiuc.edu])
 m4trace:configure.ac:50: -1- m4_pattern_forbid([^_?A[CHUM]_])
 m4trace:configure.ac:50: -1- m4_pattern_forbid([_AC_])
 m4trace:configure.ac:50: -1- m4_pattern_forbid([^LIBOBJS$], [do not use LIBOBJS directly, use AC_LIBOBJ (see section `AC_LIBOBJ vs LIBOBJS'])
diff -urN openimpact-1.0rc4/configure openimpact-1.0rc4.Limpact/configure
--- openimpact-1.0rc4/configure	2007-02-07 15:18:39.844908000 -0600
+++ openimpact-1.0rc4.Limpact/configure	2007-02-07 15:21:13.827511000 -0600
@@ -1,6 +1,6 @@
 #! /bin/sh
 # Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.54 for openimpact 1.0rc4.
+# Generated by GNU Autoconf 2.54 for openimpact 1.0rc4.Limpact.
 #
 # Report bugs to <rkidd@crhc.uiuc.edu>.
 #
@@ -265,8 +265,8 @@
 # Identity of this package.
 PACKAGE_NAME='openimpact'
 PACKAGE_TARNAME='openimpact'
-PACKAGE_VERSION='1.0rc4'
-PACKAGE_STRING='openimpact 1.0rc4'
+PACKAGE_VERSION='1.0rc4.Limpact'
+PACKAGE_STRING='openimpact 1.0rc4.Limpact'
 PACKAGE_BUGREPORT='rkidd@crhc.uiuc.edu'
 
 ac_unique_file="src/Lcode/Lcode/l_code.c"
@@ -776,7 +776,7 @@
   # Omit some internal or obsolete options to make the list less imposing.
   # This message is too long to be a string in the A/UX 3.1 sh.
   cat <<_ACEOF
-\`configure' configures openimpact 1.0rc4 to adapt to many kinds of systems.
+\`configure' configures openimpact 1.0rc4.Limpact to adapt to many kinds of systems.
 
 Usage: $0 [OPTION]... [VAR=VALUE]...
 
@@ -843,7 +843,7 @@
 
 if test -n "$ac_init_help"; then
   case $ac_init_help in
-     short | recursive ) echo "Configuration of openimpact 1.0rc4:";;
+     short | recursive ) echo "Configuration of openimpact 1.0rc4.Limpact:";;
    esac
   cat <<\_ACEOF
 
@@ -936,7 +936,7 @@
 test -n "$ac_init_help" && exit 0
 if $ac_init_version; then
   cat <<\_ACEOF
-openimpact configure 1.0rc4
+openimpact configure 1.0rc4.Limpact
 generated by GNU Autoconf 2.54
 
 Copyright 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002
@@ -951,7 +951,7 @@
 This file contains any messages produced by compilers while
 running configure, to aid debugging if configure makes a mistake.
 
-It was created by openimpact $as_me 1.0rc4, which was
+It was created by openimpact $as_me 1.0rc4.Limpact, which was
 generated by GNU Autoconf 2.54.  Invocation command line was
 
   $ $0 $@
@@ -1603,7 +1603,7 @@
 
 # Define the identity of the package.
  PACKAGE=openimpact
- VERSION=1.0rc4
+ VERSION=1.0rc4.Limpact
 
 
 cat >>confdefs.h <<_ACEOF
@@ -12812,7 +12812,7 @@
 } >&5
 cat >&5 <<_CSEOF
 
-This file was extended by openimpact $as_me 1.0rc4, which was
+This file was extended by openimpact $as_me 1.0rc4.Limpact, which was
 generated by GNU Autoconf 2.54.  Invocation command line was
 
   CONFIG_FILES    = $CONFIG_FILES
@@ -12874,7 +12874,7 @@
 
 cat >>$CONFIG_STATUS <<_ACEOF
 ac_cs_version="\\
-openimpact config.status 1.0rc4
+openimpact config.status 1.0rc4.Limpact
 configured by $0, generated by GNU Autoconf 2.54,
   with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\"
 
diff -urN openimpact-1.0rc4/configure.ac openimpact-1.0rc4.Limpact/configure.ac
--- openimpact-1.0rc4/configure.ac	2005-03-17 13:44:57.000000000 -0600
+++ openimpact-1.0rc4.Limpact/configure.ac	2005-04-26 16:24:34.000000000 -0500
@@ -47,7 +47,7 @@
 ###############################################################################
 
 # Process this file with autoconf to produce a configure script.
-AC_INIT([openimpact], [1.0rc4],  [rkidd@crhc.uiuc.edu])
+AC_INIT([openimpact], [1.0rc4.Limpact],  [rkidd@crhc.uiuc.edu])
 AC_CANONICAL_BUILD
 AC_CANONICAL_HOST
 AC_CANONICAL_TARGET
diff -urN openimpact-1.0rc4/Makefile.in openimpact-1.0rc4.Limpact/Makefile.in
--- openimpact-1.0rc4/Makefile.in	2007-02-07 15:20:10.429544883 -0600
+++ openimpact-1.0rc4.Limpact/Makefile.in	2007-02-07 15:22:43.525069866 -0600
@@ -2286,6 +2286,105 @@
 
 mdes_structure_CLN = $(mdes_structure_DATA)
 
+mdes_Limpactdir = $(prefix)/mdes/Limpact
+
+mdes_Limpact_DATA = \
+	mdes/Limpact/EPIC_1G_1BL.lmdes2 mdes/Limpact/EPIC_2G_1BL.lmdes2 \
+	mdes/Limpact/EPIC_2G_2BL.lmdes2 mdes/Limpact/EPIC_4G_1BL.lmdes2 \
+	mdes/Limpact/EPIC_4G_2BL.lmdes2 mdes/Limpact/EPIC_4G_4BL.lmdes2 \
+	mdes/Limpact/EPIC_8G_1BL.lmdes2	mdes/Limpact/EPIC_8G_2BL.lmdes2 \
+	mdes/Limpact/EPIC_8G_4BL.lmdes2 mdes/Limpact/EPIC_8G_8BL.lmdes2 \
+	mdes/Limpact/EPIC_8G_1BL_TI.lmdes2 \
+	mdes/Limpact/EPIC_8G_MIX_3BX_LDLAT3.lmdes2 \
+	mdes/Limpact/EPIC_8G_MIX_3BX.lmdes2  mdes/Limpact/EPIC_16G_1BL.lmdes2 \
+	mdes/Limpact/EPIC_16G_2BL.lmdes2 mdes/Limpact/EPIC_16G_4BL.lmdes2 \
+	mdes/Limpact/EPIC_16G_8BL.lmdes2 mdes/Limpact/EPIC_16G_16BL.lmdes2 \
+	mdes/Limpact/EPIC_1R_1BL.lmdes2 mdes/Limpact/EPIC_2R_1BL.lmdes2 \
+	mdes/Limpact/EPIC_2R_2BL.lmdes2 mdes/Limpact/EPIC_4R_1BL.lmdes2 \
+	mdes/Limpact/EPIC_4R_2BL.lmdes2 mdes/Limpact/EPIC_4R_4BL.lmdes2 \
+	mdes/Limpact/EPIC_8R_1BL.lmdes2 mdes/Limpact/EPIC_8R_2BL.lmdes2 \
+	mdes/Limpact/EPIC_8R_4BL.lmdes2 mdes/Limpact/EPIC_8R_8BL.lmdes2 \
+	mdes/Limpact/EPIC_16R_16BL.lmdes2 mdes/Limpact/EPIC_16R_1BL.lmdes2 \
+	mdes/Limpact/EPIC_16R_2BL.lmdes2 mdes/Limpact/EPIC_16R_4BL.lmdes2 \
+	mdes/Limpact/EPIC_16R_8BL.lmdes2 \
+	mdes/Limpact/IMPACT_1G.lmdes mdes/Limpact/IMPACT_1G.lmdes2 \
+	mdes/Limpact/IMPACT_2G_1BR.lmdes mdes/Limpact/IMPACT_2G_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_2G.lmdes mdes/Limpact/IMPACT_2G.lmdes2 \
+	mdes/Limpact/IMPACT_3G_1BR.lmdes mdes/Limpact/IMPACT_3G_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_3G_2BR.lmdes mdes/Limpact/IMPACT_3G_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_3G.lmdes mdes/Limpact/IMPACT_3G.lmdes2 \
+	mdes/Limpact/IMPACT_4G_1BR.lmdes mdes/Limpact/IMPACT_4G_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_4G_2BR.lmdes mdes/Limpact/IMPACT_4G_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_4G.lmdes mdes/Limpact/IMPACT_4G.lmdes2 \
+	mdes/Limpact/IMPACT_8G_1BR.lmdes mdes/Limpact/IMPACT_8G_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_8G_2BR.lmdes mdes/Limpact/IMPACT_8G_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_8G_4BR.lmdes mdes/Limpact/IMPACT_8G_4BR.lmdes2 \
+	mdes/Limpact/IMPACT_8G.lmdes mdes/Limpact/IMPACT_8G.lmdes2 \
+	mdes/Limpact/IMPACT_16G_1BR.lmdes mdes/Limpact/IMPACT_16G_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_16G_2BR.lmdes mdes/Limpact/IMPACT_16G_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_16G_4BR.lmdes mdes/Limpact/IMPACT_16G_4BR.lmdes2 \
+	mdes/Limpact/IMPACT_16G_8BR.lmdes mdes/Limpact/IMPACT_16G_8BR.lmdes2 \
+	mdes/Limpact/IMPACT_16G.lmdes mdes/Limpact/IMPACT_16G.lmdes2 \
+	mdes/Limpact/IMPACT_1R.lmdes mdes/Limpact/IMPACT_1R.lmdes2 \
+	mdes/Limpact/IMPACT_2R_1BR.lmdes mdes/Limpact/IMPACT_2R_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_2R.lmdes mdes/Limpact/IMPACT_2R.lmdes2 \
+	mdes/Limpact/IMPACT_4R_1BR.lmdes mdes/Limpact/IMPACT_4R_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_4R_2BR.lmdes mdes/Limpact/IMPACT_4R_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_4R.lmdes mdes/Limpact/IMPACT_4R.lmdes2 \
+	mdes/Limpact/IMPACT_8R_1BR.lmdes mdes/Limpact/IMPACT_8R_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_8R_2BR.lmdes mdes/Limpact/IMPACT_8R_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_8R_4BR.lmdes mdes/Limpact/IMPACT_8R_4BR.lmdes2 \
+	mdes/Limpact/IMPACT_8R.lmdes mdes/Limpact/IMPACT_8R.lmdes2 \
+	mdes/Limpact/IMPACT_16R_1BR.lmdes mdes/Limpact/IMPACT_16R_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_16R_2BR.lmdes mdes/Limpact/IMPACT_16R_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_16R_4BR.lmdes mdes/Limpact/IMPACT_16R_4BR.lmdes2 \
+	mdes/Limpact/IMPACT_16R_8BR.lmdes mdes/Limpact/IMPACT_16R_8BR.lmdes2 \
+	mdes/Limpact/IMPACT_16R.lmdes mdes/Limpact/IMPACT_16R.lmdes2 \
+	mdes/Limpact/SS_1G_1BL.lmdes2 mdes/Limpact/SS_1G_1BX.lmdes2 \
+	mdes/Limpact/SS_2G_1BL.lmdes2 mdes/Limpact/SS_2G_1BX.lmdes2 \
+	mdes/Limpact/SS_2G_2BL.lmdes2 mdes/Limpact/SS_2G_2BX.lmdes2 \
+	mdes/Limpact/SS_4G_1BL.lmdes2 mdes/Limpact/SS_4G_1BX.lmdes2 \
+	mdes/Limpact/SS_4G_2BL.lmdes2 mdes/Limpact/SS_4G_2BX.lmdes2 \
+	mdes/Limpact/SS_4G_4BL.lmdes2 mdes/Limpact/SS_4G_4BX.lmdes2 \
+	mdes/Limpact/SS_8G_1BL.lmdes2 mdes/Limpact/SS_8G_1BX.lmdes2 \
+	mdes/Limpact/SS_8G_2BL.lmdes2 mdes/Limpact/SS_8G_2BX.lmdes2 \
+	mdes/Limpact/SS_8G_4BL.lmdes2 mdes/Limpact/SS_8G_4BX.lmdes2 \
+	mdes/Limpact/SS_8G_8BL.lmdes2 mdes/Limpact/SS_8G_8BX.lmdes2 \
+	mdes/Limpact/SS_16G_1BL.lmdes2 mdes/Limpact/SS_16G_1BX.lmdes2 \
+	mdes/Limpact/SS_16G_2BL.lmdes2 mdes/Limpact/SS_16G_2BX.lmdes2 \
+	mdes/Limpact/SS_16G_4BL.lmdes2 mdes/Limpact/SS_16G_4BX.lmdes2 \
+	mdes/Limpact/SS_16G_8BL.lmdes2 mdes/Limpact/SS_16G_8BX.lmdes2 \
+	mdes/Limpact/SS_16G_16BL.lmdes2 mdes/Limpact/SS_16G_16BX.lmdes2 \
+	mdes/Limpact/SS_1R_1BL.lmdes2 mdes/Limpact/SS_1R_1BX.lmdes2 \
+	mdes/Limpact/SS_2R_1BL.lmdes2 mdes/Limpact/SS_2R_1BX.lmdes2 \
+	mdes/Limpact/SS_2R_2BL.lmdes2 mdes/Limpact/SS_2R_2BX.lmdes2 \
+	mdes/Limpact/SS_4R_1BL.lmdes2 mdes/Limpact/SS_4R_1BX.lmdes2 \
+	mdes/Limpact/SS_4R_2BL.lmdes2 mdes/Limpact/SS_4R_2BX.lmdes2 \
+	mdes/Limpact/SS_4R_4BL.lmdes2 mdes/Limpact/SS_4R_4BX.lmdes2 \
+	mdes/Limpact/SS_8R_1BL.lmdes2 mdes/Limpact/SS_8R_1BX.lmdes2 \
+	mdes/Limpact/SS_8R_2BL.lmdes2 mdes/Limpact/SS_8R_2BX.lmdes2 \
+	mdes/Limpact/SS_8R_4BL.lmdes2 mdes/Limpact/SS_8R_4BX.lmdes2 \
+	mdes/Limpact/SS_8R_8BL.lmdes2 mdes/Limpact/SS_8R_8BX.lmdes2 \
+	mdes/Limpact/SS_16R_1BL.lmdes2 mdes/Limpact/SS_16R_1BX.lmdes2 \
+	mdes/Limpact/SS_16R_2BL.lmdes2 mdes/Limpact/SS_16R_2BX.lmdes2 \
+	mdes/Limpact/SS_16R_4BL.lmdes2 mdes/Limpact/SS_16R_4BX.lmdes2 \
+	mdes/Limpact/SS_16R_8BL.lmdes2 mdes/Limpact/SS_16R_8BX.lmdes2 \
+	mdes/Limpact/SS_16R_16BL.lmdes2 mdes/Limpact/SS_16R_16BX.lmdes2
+
+dist_mdes_Limpact_DATA = mdes/Limpact/EPIC_8G_1BL_TI.hmdes2 \
+			 mdes/Limpact/IMPACT_BASE_TEMPLATE.hmdes2 \
+			 mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+			 mdes/Limpact/IMPACT_GEN_NEWPRED_BASE.hmdes \
+			 mdes/Limpact/IMPACT_IA64_TEMPLATE.hmdes2 \
+			 mdes/Limpact/IMPACT_RES_BASE.hmdes \
+			 mdes/Limpact/IMPACT_RES_NEWPRED_BASE.hmdes \
+			 mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+			 mdes/Limpact/PACT_BASE_TEMPLATE.hmdes2 \
+			 mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2
+
+
+mdes_Limpact_CLN = $(mdes_Limpact_DATA)
+
 mdes_Ltahoedir = $(prefix)/mdes/Ltahoe
 
 mdes_Ltahoe_DATA = \
@@ -2301,7 +2400,7 @@
 mdes_Ltahoe_CLN = $(mdes_Ltahoe_DATA)
 
 mdes_CLN = \
-	$(mdes_structure_CLN)  $(mdes_Ltahoe_CLN) 
+	$(mdes_structure_CLN) $(mdes_Limpact_CLN) $(mdes_Ltahoe_CLN) 
 
 
 platform_hp_cc_includedir = $(prefix)/platform/hp_cc/include
@@ -4607,9 +4706,10 @@
 	$(src_machine_md_compiler_md_compiler_SOURCES) \
 	$(src_machine_md_preprocessor_md_preprocessor_SOURCES)
 DATA = $(dist_benchmarks_NONE_DATA) $(dist_driver_DATA) \
-	$(dist_intrinsic_lib_DATA) $(dist_mdes_Ltahoe_DATA) \
-	$(dist_mdes_structure_DATA) $(dist_parms_DATA) \
-	$(dist_platform_hp_cc_DATA) $(dist_platform_hp_cc_include_DATA) \
+	$(dist_intrinsic_lib_DATA) $(dist_mdes_Limpact_DATA) \
+	$(dist_mdes_Ltahoe_DATA) $(dist_mdes_structure_DATA) \
+	$(dist_parms_DATA) $(dist_platform_hp_cc_DATA) \
+	$(dist_platform_hp_cc_include_DATA) \
 	$(dist_platform_ia64lin_gcc_DATA) \
 	$(dist_platform_ia64lin_gcc_include_DATA) \
 	$(dist_platform_x86lin_gcc_DATA) \
@@ -4617,7 +4717,7 @@
 	$(dist_platform_x86lin_gcc_include__newgcc_DATA) \
 	$(dist_platform_x86lin_gcc_include_bits_DATA) \
 	$(dist_projects_full_DATA) $(intrinsic_lib_DATA) \
-	$(mdes_Ltahoe_DATA) $(mdes_structure_DATA) \
+	$(mdes_Limpact_DATA) $(mdes_Ltahoe_DATA) $(mdes_structure_DATA) \
 	$(platform_hp_cc_DATA) $(platform_ia64lin_gcc_DATA) \
 	$(platform_ia64lin_gcc_IPA_lib_DATA) \
 	$(platform_x86lin_gcc_DATA) $(platform_x86lin_gcc_IPA_lib_DATA)
@@ -4627,9 +4727,10 @@
 	$(nodist_src_library_HEADERS)
 
 DIST_COMMON = $(dist_benchmarks_NONE_DATA) $(dist_driver_DATA) \
-	$(dist_intrinsic_lib_DATA) $(dist_mdes_Ltahoe_DATA) \
-	$(dist_mdes_structure_DATA) $(dist_parms_DATA) \
-	$(dist_platform_hp_cc_DATA) $(dist_platform_hp_cc_include_DATA) \
+	$(dist_intrinsic_lib_DATA) $(dist_mdes_Limpact_DATA) \
+	$(dist_mdes_Ltahoe_DATA) $(dist_mdes_structure_DATA) \
+	$(dist_parms_DATA) $(dist_platform_hp_cc_DATA) \
+	$(dist_platform_hp_cc_include_DATA) \
 	$(dist_platform_ia64lin_gcc_DATA) \
 	$(dist_platform_ia64lin_gcc_include_DATA) \
 	$(dist_platform_x86lin_gcc_DATA) \
@@ -4644,6 +4745,7 @@
 	$(srcdir)/inhouse/ia64_tools/Makefile.am \
 	$(srcdir)/inhouse/ia64_tools/chatr/Makefile.am \
 	$(srcdir)/intrinsic.lib/Makefile.am \
+	$(srcdir)/mdes/Limpact/Makefile.am \
 	$(srcdir)/mdes/Ltahoe/Makefile.am $(srcdir)/mdes/Makefile.am \
 	$(srcdir)/mdes/structure/Makefile.am \
 	$(srcdir)/parms/Makefile.am $(srcdir)/platform/Makefile.am \
@@ -4736,7 +4838,7 @@
 
 am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \
  configure.lineno
-$(srcdir)/Makefile.in:  Makefile.am $(srcdir)/src/Makefile.am $(srcdir)/src/bdd/Makefile.am $(srcdir)/src/library/Makefile.am $(srcdir)/src/machine/Makefile.am $(srcdir)/src/machine/Lmdes/Makefile.am $(srcdir)/src/machine/hmdes/Makefile.am $(srcdir)/src/machine/Mspec/Makefile.am $(srcdir)/src/machine/Lmdes_build/Makefile.am $(srcdir)/src/machine/convert_hmdes/Makefile.am $(srcdir)/src/machine/lmdes2_customizer/Makefile.am $(srcdir)/src/machine/md_compiler/Makefile.am $(srcdir)/src/machine/md_preprocessor/Makefile.am $(srcdir)/src/Lcode/Makefile.am $(srcdir)/src/Lcode/Lcode/Makefile.am $(srcdir)/src/Lcode/codegen/Makefile.am $(srcdir)/src/Lcode/codegen/Lschedule/Makefile.am $(srcdir)/src/Lcode/codegen/Regalloc/Makefile.am $(srcdir)/src/Lcode/codegen/Mopti/Makefile.am $(srcdir)/src/Lcode/codegen/Lsoftpipe/Makefile.am $(srcdir)/src/Lcode/codegen/Mopti-ia64/Makefile.am $(srcdir)/src/Lcode/codegen/Ltahoe/Makefile.am $(srcdir)/src/Lcode/codegen/Limpact/Makefile.am $(srcdir)/src/Lcode/opti/Makefile.am $(srcdir)/src/Lcode/opti/Lmarkpipe/Makefile.am $(srcdir)/src/Lcode/opti/Lblock/Makefile.am $(srcdir)/src/Lcode/opti/Lopti/Makefile.am $(srcdir)/src/Lcode/opti/Lsuperscalar/Makefile.am $(srcdir)/src/Lcode/opti/Lsafe/Makefile.am $(srcdir)/src/Lcode/performance/Makefile.am $(srcdir)/src/Lcode/performance/Lprobe/Makefile.am $(srcdir)/src/Lcode/performance/Lencode/Makefile.am $(srcdir)/src/Lcode/performance/Lget/Makefile.am $(srcdir)/src/Lcode/performance/Lprofile/Makefile.am $(srcdir)/src/Lcode/tools/Makefile.am $(srcdir)/src/Lcode/tools/Lbuild_prototype_info/Makefile.am $(srcdir)/src/Lcode/tools/Lemulate/Makefile.am $(srcdir)/src/Lcode/tools/Lstatic/Makefile.am $(srcdir)/src/Lcode/tools/Lsplit/Makefile.am $(srcdir)/src/Lcode/tools/Lgp_rel/Makefile.am $(srcdir)/src/Lcode/tools/Linduct/Makefile.am $(srcdir)/src/Lcode/tools/Lsplit_cbs/Makefile.am $(srcdir)/src/Lcode/sched/Makefile.am $(srcdir)/src/Lcode/sched/SM/Makefile.am $(srcdir)/src/Pcode/Makefile.am $(srcdir)/src/Pcode/Pannotate/Makefile.am $(srcdir)/src/Pcode/Pcode/Makefile.am $(srcdir)/src/Pcode/Pflatten/Makefile.am $(srcdir)/src/Pcode/Pinline/Makefile.am $(srcdir)/src/Pcode/Pipa/Makefile.am $(srcdir)/src/Pcode/Plib_CF/Makefile.am $(srcdir)/src/Pcode/Plib_DD/Makefile.am $(srcdir)/src/Pcode/Plib_probe/Makefile.am $(srcdir)/src/Pcode/Plib_SS/Makefile.am $(srcdir)/src/Pcode/Plink/Makefile.am $(srcdir)/src/Pcode/Pmerge_iter/Makefile.am $(srcdir)/src/Pcode/Pmerge_prof/Makefile.am $(srcdir)/src/Pcode/Pomega/Makefile.am $(srcdir)/src/Pcode/Protate/Makefile.am $(srcdir)/src/Pcode/Psymtab/Makefile.am $(srcdir)/src/Pcode/PtoC/Makefile.am $(srcdir)/src/Pcode/PtoL/Makefile.am $(srcdir)/src/Pcode/PtoNM/Makefile.am $(srcdir)/inhouse/Makefile.am $(srcdir)/inhouse/dumpelfsection/Makefile.am $(srcdir)/inhouse/edgcpfe/Makefile.am $(srcdir)/inhouse/ia64_tools/Makefile.am $(srcdir)/inhouse/ia64_tools/chatr/Makefile.am $(srcdir)/mdes/Makefile.am $(srcdir)/mdes/structure/Makefile.am $(srcdir)/mdes/Ltahoe/Makefile.am $(srcdir)/platform/Makefile.am $(srcdir)/platform/hp_cc/Makefile.am $(srcdir)/platform/hp_cc/include/Makefile.am $(srcdir)/platform/ia64lin_gcc/Makefile.am $(srcdir)/platform/ia64lin_gcc/include/Makefile.am $(srcdir)/platform/ia64lin_gcc/IPA_lib/Makefile.am $(srcdir)/platform/x86lin_gcc/Makefile.am $(srcdir)/platform/x86lin_gcc/include/Makefile.am $(srcdir)/platform/x86lin_gcc/include/bits/Makefile.am $(srcdir)/platform/x86lin_gcc/include/_newgcc/Makefile.am $(srcdir)/platform/x86lin_gcc/IPA_lib/Makefile.am $(srcdir)/scripts/Makefile.am $(srcdir)/parms/Makefile.am $(srcdir)/intrinsic.lib/Makefile.am $(srcdir)/driver/Makefile.am $(srcdir)/benchmarks/Makefile.am $(srcdir)/benchmarks/NONE/Makefile.am $(srcdir)/projects/Makefile.am $(srcdir)/projects/full/Makefile.am $(srcdir)/doc/Makefile.am $(top_srcdir)/configure.ac $(ACLOCAL_M4)
+$(srcdir)/Makefile.in:  Makefile.am $(srcdir)/src/Makefile.am $(srcdir)/src/bdd/Makefile.am $(srcdir)/src/library/Makefile.am $(srcdir)/src/machine/Makefile.am $(srcdir)/src/machine/Lmdes/Makefile.am $(srcdir)/src/machine/hmdes/Makefile.am $(srcdir)/src/machine/Mspec/Makefile.am $(srcdir)/src/machine/Lmdes_build/Makefile.am $(srcdir)/src/machine/convert_hmdes/Makefile.am $(srcdir)/src/machine/lmdes2_customizer/Makefile.am $(srcdir)/src/machine/md_compiler/Makefile.am $(srcdir)/src/machine/md_preprocessor/Makefile.am $(srcdir)/src/Lcode/Makefile.am $(srcdir)/src/Lcode/Lcode/Makefile.am $(srcdir)/src/Lcode/codegen/Makefile.am $(srcdir)/src/Lcode/codegen/Lschedule/Makefile.am $(srcdir)/src/Lcode/codegen/Regalloc/Makefile.am $(srcdir)/src/Lcode/codegen/Mopti/Makefile.am $(srcdir)/src/Lcode/codegen/Lsoftpipe/Makefile.am $(srcdir)/src/Lcode/codegen/Mopti-ia64/Makefile.am $(srcdir)/src/Lcode/codegen/Ltahoe/Makefile.am $(srcdir)/src/Lcode/codegen/Limpact/Makefile.am $(srcdir)/src/Lcode/opti/Makefile.am $(srcdir)/src/Lcode/opti/Lmarkpipe/Makefile.am $(srcdir)/src/Lcode/opti/Lblock/Makefile.am $(srcdir)/src/Lcode/opti/Lopti/Makefile.am $(srcdir)/src/Lcode/opti/Lsuperscalar/Makefile.am $(srcdir)/src/Lcode/opti/Lsafe/Makefile.am $(srcdir)/src/Lcode/performance/Makefile.am $(srcdir)/src/Lcode/performance/Lprobe/Makefile.am $(srcdir)/src/Lcode/performance/Lencode/Makefile.am $(srcdir)/src/Lcode/performance/Lget/Makefile.am $(srcdir)/src/Lcode/performance/Lprofile/Makefile.am $(srcdir)/src/Lcode/tools/Makefile.am $(srcdir)/src/Lcode/tools/Lbuild_prototype_info/Makefile.am $(srcdir)/src/Lcode/tools/Lemulate/Makefile.am $(srcdir)/src/Lcode/tools/Lstatic/Makefile.am $(srcdir)/src/Lcode/tools/Lsplit/Makefile.am $(srcdir)/src/Lcode/tools/Lgp_rel/Makefile.am $(srcdir)/src/Lcode/tools/Linduct/Makefile.am $(srcdir)/src/Lcode/tools/Lsplit_cbs/Makefile.am $(srcdir)/src/Lcode/sched/Makefile.am $(srcdir)/src/Lcode/sched/SM/Makefile.am $(srcdir)/src/Pcode/Makefile.am $(srcdir)/src/Pcode/Pannotate/Makefile.am $(srcdir)/src/Pcode/Pcode/Makefile.am $(srcdir)/src/Pcode/Pflatten/Makefile.am $(srcdir)/src/Pcode/Pinline/Makefile.am $(srcdir)/src/Pcode/Pipa/Makefile.am $(srcdir)/src/Pcode/Plib_CF/Makefile.am $(srcdir)/src/Pcode/Plib_DD/Makefile.am $(srcdir)/src/Pcode/Plib_probe/Makefile.am $(srcdir)/src/Pcode/Plib_SS/Makefile.am $(srcdir)/src/Pcode/Plink/Makefile.am $(srcdir)/src/Pcode/Pmerge_iter/Makefile.am $(srcdir)/src/Pcode/Pmerge_prof/Makefile.am $(srcdir)/src/Pcode/Pomega/Makefile.am $(srcdir)/src/Pcode/Protate/Makefile.am $(srcdir)/src/Pcode/Psymtab/Makefile.am $(srcdir)/src/Pcode/PtoC/Makefile.am $(srcdir)/src/Pcode/PtoL/Makefile.am $(srcdir)/src/Pcode/PtoNM/Makefile.am $(srcdir)/inhouse/Makefile.am $(srcdir)/inhouse/dumpelfsection/Makefile.am $(srcdir)/inhouse/edgcpfe/Makefile.am $(srcdir)/inhouse/ia64_tools/Makefile.am $(srcdir)/inhouse/ia64_tools/chatr/Makefile.am $(srcdir)/mdes/Makefile.am $(srcdir)/mdes/structure/Makefile.am $(srcdir)/mdes/Limpact/Makefile.am $(srcdir)/mdes/Ltahoe/Makefile.am $(srcdir)/platform/Makefile.am $(srcdir)/platform/hp_cc/Makefile.am $(srcdir)/platform/hp_cc/include/Makefile.am $(srcdir)/platform/ia64lin_gcc/Makefile.am $(srcdir)/platform/ia64lin_gcc/include/Makefile.am $(srcdir)/platform/ia64lin_gcc/IPA_lib/Makefile.am $(srcdir)/platform/x86lin_gcc/Makefile.am $(srcdir)/platform/x86lin_gcc/include/Makefile.am $(srcdir)/platform/x86lin_gcc/include/bits/Makefile.am $(srcdir)/platform/x86lin_gcc/include/_newgcc/Makefile.am $(srcdir)/platform/x86lin_gcc/IPA_lib/Makefile.am $(srcdir)/scripts/Makefile.am $(srcdir)/parms/Makefile.am $(srcdir)/intrinsic.lib/Makefile.am $(srcdir)/driver/Makefile.am $(srcdir)/benchmarks/Makefile.am $(srcdir)/benchmarks/NONE/Makefile.am $(srcdir)/projects/Makefile.am $(srcdir)/projects/full/Makefile.am $(srcdir)/doc/Makefile.am $(top_srcdir)/configure.ac $(ACLOCAL_M4)
 	cd $(top_srcdir) && \
 	  $(AUTOMAKE) --foreign  Makefile
 Makefile:  $(srcdir)/Makefile.in  $(top_builddir)/config.status
@@ -20330,6 +20432,24 @@
 	  echo " rm -f $(DESTDIR)$(intrinsic_libdir)/$$f"; \
 	  rm -f $(DESTDIR)$(intrinsic_libdir)/$$f; \
 	done
+dist_mdes_LimpactDATA_INSTALL = $(INSTALL_DATA)
+install-dist_mdes_LimpactDATA: $(dist_mdes_Limpact_DATA)
+	@$(NORMAL_INSTALL)
+	$(mkinstalldirs) $(DESTDIR)$(mdes_Limpactdir)
+	@list='$(dist_mdes_Limpact_DATA)'; for p in $$list; do \
+	  if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+	  f="`echo $$p | sed -e 's|^.*/||'`"; \
+	  echo " $(dist_mdes_LimpactDATA_INSTALL) $$d$$p $(DESTDIR)$(mdes_Limpactdir)/$$f"; \
+	  $(dist_mdes_LimpactDATA_INSTALL) $$d$$p $(DESTDIR)$(mdes_Limpactdir)/$$f; \
+	done
+
+uninstall-dist_mdes_LimpactDATA:
+	@$(NORMAL_UNINSTALL)
+	@list='$(dist_mdes_Limpact_DATA)'; for p in $$list; do \
+	  f="`echo $$p | sed -e 's|^.*/||'`"; \
+	  echo " rm -f $(DESTDIR)$(mdes_Limpactdir)/$$f"; \
+	  rm -f $(DESTDIR)$(mdes_Limpactdir)/$$f; \
+	done
 dist_mdes_LtahoeDATA_INSTALL = $(INSTALL_DATA)
 install-dist_mdes_LtahoeDATA: $(dist_mdes_Ltahoe_DATA)
 	@$(NORMAL_INSTALL)
@@ -20564,6 +20684,24 @@
 	  echo " rm -f $(DESTDIR)$(intrinsic_libdir)/$$f"; \
 	  rm -f $(DESTDIR)$(intrinsic_libdir)/$$f; \
 	done
+mdes_LimpactDATA_INSTALL = $(INSTALL_DATA)
+install-mdes_LimpactDATA: $(mdes_Limpact_DATA)
+	@$(NORMAL_INSTALL)
+	$(mkinstalldirs) $(DESTDIR)$(mdes_Limpactdir)
+	@list='$(mdes_Limpact_DATA)'; for p in $$list; do \
+	  if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+	  f="`echo $$p | sed -e 's|^.*/||'`"; \
+	  echo " $(mdes_LimpactDATA_INSTALL) $$d$$p $(DESTDIR)$(mdes_Limpactdir)/$$f"; \
+	  $(mdes_LimpactDATA_INSTALL) $$d$$p $(DESTDIR)$(mdes_Limpactdir)/$$f; \
+	done
+
+uninstall-mdes_LimpactDATA:
+	@$(NORMAL_UNINSTALL)
+	@list='$(mdes_Limpact_DATA)'; for p in $$list; do \
+	  f="`echo $$p | sed -e 's|^.*/||'`"; \
+	  echo " rm -f $(DESTDIR)$(mdes_Limpactdir)/$$f"; \
+	  rm -f $(DESTDIR)$(mdes_Limpactdir)/$$f; \
+	done
 mdes_LtahoeDATA_INSTALL = $(INSTALL_DATA)
 install-mdes_LtahoeDATA: $(mdes_Ltahoe_DATA)
 	@$(NORMAL_INSTALL)
@@ -20797,7 +20935,7 @@
 distdir: $(DISTFILES)
 	$(am__remove_distdir)
 	mkdir $(distdir)
-	$(mkinstalldirs) $(distdir)/./benchmarks $(distdir)/./benchmarks/NONE $(distdir)/./doc $(distdir)/./driver $(distdir)/./include $(distdir)/./inhouse $(distdir)/./inhouse/dumpelfsection $(distdir)/./inhouse/edgcpfe $(distdir)/./inhouse/ia64_tools $(distdir)/./inhouse/ia64_tools/chatr $(distdir)/./intrinsic.lib $(distdir)/./mdes $(distdir)/./mdes/Ltahoe $(distdir)/./mdes/structure $(distdir)/./parms $(distdir)/./platform $(distdir)/./platform/hp_cc $(distdir)/./platform/hp_cc/include $(distdir)/./platform/ia64lin_gcc $(distdir)/./platform/ia64lin_gcc/IPA_lib $(distdir)/./platform/ia64lin_gcc/include $(distdir)/./platform/x86lin_gcc $(distdir)/./platform/x86lin_gcc/IPA_lib $(distdir)/./platform/x86lin_gcc/include $(distdir)/./platform/x86lin_gcc/include/_newgcc $(distdir)/./platform/x86lin_gcc/include/bits $(distdir)/./projects $(distdir)/./projects/full $(distdir)/./scripts $(distdir)/./src $(distdir)/./src/Lcode $(distdir)/./src/Lcode/Lcode $(distdir)/./src/Lcode/codegen $(distdir)/./src/Lcode/codegen/Limpact $(distdir)/./src/Lcode/codegen/Lschedule $(distdir)/./src/Lcode/codegen/Lsoftpipe $(distdir)/./src/Lcode/codegen/Ltahoe $(distdir)/./src/Lcode/codegen/Mopti $(distdir)/./src/Lcode/codegen/Mopti-ia64 $(distdir)/./src/Lcode/codegen/Regalloc $(distdir)/./src/Lcode/opti $(distdir)/./src/Lcode/opti/Lblock $(distdir)/./src/Lcode/opti/Lmarkpipe $(distdir)/./src/Lcode/opti/Lopti $(distdir)/./src/Lcode/opti/Lsafe $(distdir)/./src/Lcode/opti/Lsuperscalar $(distdir)/./src/Lcode/performance $(distdir)/./src/Lcode/performance/Lencode $(distdir)/./src/Lcode/performance/Lget $(distdir)/./src/Lcode/performance/Lprobe $(distdir)/./src/Lcode/performance/Lprofile $(distdir)/./src/Lcode/sched $(distdir)/./src/Lcode/sched/SM $(distdir)/./src/Lcode/tools $(distdir)/./src/Lcode/tools/Lbuild_prototype_info $(distdir)/./src/Lcode/tools/Lemulate $(distdir)/./src/Lcode/tools/Lgp_rel $(distdir)/./src/Lcode/tools/Linduct $(distdir)/./src/Lcode/tools/Lsplit $(distdir)/./src/Lcode/tools/Lsplit_cbs $(distdir)/./src/Lcode/tools/Lstatic $(distdir)/./src/Pcode $(distdir)/./src/Pcode/Pannotate $(distdir)/./src/Pcode/Pcode $(distdir)/./src/Pcode/Pflatten $(distdir)/./src/Pcode/Pinline $(distdir)/./src/Pcode/Pipa $(distdir)/./src/Pcode/Plib_CF $(distdir)/./src/Pcode/Plib_DD $(distdir)/./src/Pcode/Plib_SS $(distdir)/./src/Pcode/Plib_probe $(distdir)/./src/Pcode/Plink $(distdir)/./src/Pcode/Pmerge_iter $(distdir)/./src/Pcode/Pmerge_prof $(distdir)/./src/Pcode/Pomega $(distdir)/./src/Pcode/Protate $(distdir)/./src/Pcode/Psymtab $(distdir)/./src/Pcode/PtoC $(distdir)/./src/Pcode/PtoL $(distdir)/./src/Pcode/PtoNM $(distdir)/./src/bdd $(distdir)/./src/library $(distdir)/./src/machine $(distdir)/./src/machine/Lmdes $(distdir)/./src/machine/Lmdes_build $(distdir)/./src/machine/Mspec $(distdir)/./src/machine/convert_hmdes $(distdir)/./src/machine/hmdes $(distdir)/./src/machine/lmdes2_customizer $(distdir)/./src/machine/md_compiler $(distdir)/./src/machine/md_preprocessor $(distdir)/benchmarks/NONE $(distdir)/doc $(distdir)/driver $(distdir)/intrinsic.lib $(distdir)/mdes/Ltahoe $(distdir)/mdes/structure $(distdir)/parms $(distdir)/platform $(distdir)/platform/hp_cc $(distdir)/platform/hp_cc/include $(distdir)/platform/ia64lin_gcc $(distdir)/platform/x86lin_gcc $(distdir)/platform/x86lin_gcc/include/_newgcc $(distdir)/platform/x86lin_gcc/include/bits $(distdir)/projects/full $(distdir)/scripts $(distdir)/src $(distdir)/src/Lcode/Lcode $(distdir)/src/Lcode/codegen/Limpact $(distdir)/src/Lcode/codegen/Lschedule $(distdir)/src/Lcode/codegen/Lsoftpipe $(distdir)/src/Lcode/codegen/Ltahoe $(distdir)/src/Lcode/codegen/Mopti $(distdir)/src/Lcode/codegen/Mopti-ia64 $(distdir)/src/Lcode/codegen/Regalloc $(distdir)/src/Lcode/opti/Lblock $(distdir)/src/Lcode/opti/Lmarkpipe $(distdir)/src/Lcode/opti/Lopti $(distdir)/src/Lcode/opti/Lsafe $(distdir)/src/Lcode/opti/Lsuperscalar $(distdir)/src/Lcode/performance/Lencode $(distdir)/src/Lcode/performance/Lget $(distdir)/src/Lcode/performance/Lprobe $(distdir)/src/Lcode/performance/Lprofile $(distdir)/src/Lcode/sched/SM $(distdir)/src/Lcode/tools/Lbuild_prototype_info $(distdir)/src/Lcode/tools/Lemulate $(distdir)/src/Lcode/tools/Lgp_rel $(distdir)/src/Lcode/tools/Linduct $(distdir)/src/Lcode/tools/Lsplit $(distdir)/src/Lcode/tools/Lsplit_cbs $(distdir)/src/Lcode/tools/Lstatic $(distdir)/src/Pcode/Pannotate $(distdir)/src/Pcode/Pcode $(distdir)/src/Pcode/Pflatten $(distdir)/src/Pcode/Pinline $(distdir)/src/Pcode/Pipa $(distdir)/src/Pcode/Plib_CF $(distdir)/src/Pcode/Plib_DD $(distdir)/src/Pcode/Plib_SS $(distdir)/src/Pcode/Plib_probe $(distdir)/src/Pcode/Plink $(distdir)/src/Pcode/Pmerge_iter $(distdir)/src/Pcode/Pmerge_prof $(distdir)/src/Pcode/Pomega $(distdir)/src/Pcode/Protate $(distdir)/src/Pcode/Psymtab $(distdir)/src/Pcode/PtoC $(distdir)/src/Pcode/PtoL $(distdir)/src/Pcode/PtoNM $(distdir)/src/bdd $(distdir)/src/library $(distdir)/src/machine/Lmdes $(distdir)/src/machine/Lmdes_build $(distdir)/src/machine/Mspec $(distdir)/src/machine/convert_hmdes $(distdir)/src/machine/hmdes $(distdir)/src/machine/lmdes2_customizer $(distdir)/src/machine/md_compiler $(distdir)/src/machine/md_preprocessor
+	$(mkinstalldirs) $(distdir)/./benchmarks $(distdir)/./benchmarks/NONE $(distdir)/./doc $(distdir)/./driver $(distdir)/./include $(distdir)/./inhouse $(distdir)/./inhouse/dumpelfsection $(distdir)/./inhouse/edgcpfe $(distdir)/./inhouse/ia64_tools $(distdir)/./inhouse/ia64_tools/chatr $(distdir)/./intrinsic.lib $(distdir)/./mdes $(distdir)/./mdes/Limpact $(distdir)/./mdes/Ltahoe $(distdir)/./mdes/structure $(distdir)/./parms $(distdir)/./platform $(distdir)/./platform/hp_cc $(distdir)/./platform/hp_cc/include $(distdir)/./platform/ia64lin_gcc $(distdir)/./platform/ia64lin_gcc/IPA_lib $(distdir)/./platform/ia64lin_gcc/include $(distdir)/./platform/x86lin_gcc $(distdir)/./platform/x86lin_gcc/IPA_lib $(distdir)/./platform/x86lin_gcc/include $(distdir)/./platform/x86lin_gcc/include/_newgcc $(distdir)/./platform/x86lin_gcc/include/bits $(distdir)/./projects $(distdir)/./projects/full $(distdir)/./scripts $(distdir)/./src $(distdir)/./src/Lcode $(distdir)/./src/Lcode/Lcode $(distdir)/./src/Lcode/codegen $(distdir)/./src/Lcode/codegen/Limpact $(distdir)/./src/Lcode/codegen/Lschedule $(distdir)/./src/Lcode/codegen/Lsoftpipe $(distdir)/./src/Lcode/codegen/Ltahoe $(distdir)/./src/Lcode/codegen/Mopti $(distdir)/./src/Lcode/codegen/Mopti-ia64 $(distdir)/./src/Lcode/codegen/Regalloc $(distdir)/./src/Lcode/opti $(distdir)/./src/Lcode/opti/Lblock $(distdir)/./src/Lcode/opti/Lmarkpipe $(distdir)/./src/Lcode/opti/Lopti $(distdir)/./src/Lcode/opti/Lsafe $(distdir)/./src/Lcode/opti/Lsuperscalar $(distdir)/./src/Lcode/performance $(distdir)/./src/Lcode/performance/Lencode $(distdir)/./src/Lcode/performance/Lget $(distdir)/./src/Lcode/performance/Lprobe $(distdir)/./src/Lcode/performance/Lprofile $(distdir)/./src/Lcode/sched $(distdir)/./src/Lcode/sched/SM $(distdir)/./src/Lcode/tools $(distdir)/./src/Lcode/tools/Lbuild_prototype_info $(distdir)/./src/Lcode/tools/Lemulate $(distdir)/./src/Lcode/tools/Lgp_rel $(distdir)/./src/Lcode/tools/Linduct $(distdir)/./src/Lcode/tools/Lsplit $(distdir)/./src/Lcode/tools/Lsplit_cbs $(distdir)/./src/Lcode/tools/Lstatic $(distdir)/./src/Pcode $(distdir)/./src/Pcode/Pannotate $(distdir)/./src/Pcode/Pcode $(distdir)/./src/Pcode/Pflatten $(distdir)/./src/Pcode/Pinline $(distdir)/./src/Pcode/Pipa $(distdir)/./src/Pcode/Plib_CF $(distdir)/./src/Pcode/Plib_DD $(distdir)/./src/Pcode/Plib_SS $(distdir)/./src/Pcode/Plib_probe $(distdir)/./src/Pcode/Plink $(distdir)/./src/Pcode/Pmerge_iter $(distdir)/./src/Pcode/Pmerge_prof $(distdir)/./src/Pcode/Pomega $(distdir)/./src/Pcode/Protate $(distdir)/./src/Pcode/Psymtab $(distdir)/./src/Pcode/PtoC $(distdir)/./src/Pcode/PtoL $(distdir)/./src/Pcode/PtoNM $(distdir)/./src/bdd $(distdir)/./src/library $(distdir)/./src/machine $(distdir)/./src/machine/Lmdes $(distdir)/./src/machine/Lmdes_build $(distdir)/./src/machine/Mspec $(distdir)/./src/machine/convert_hmdes $(distdir)/./src/machine/hmdes $(distdir)/./src/machine/lmdes2_customizer $(distdir)/./src/machine/md_compiler $(distdir)/./src/machine/md_preprocessor $(distdir)/benchmarks/NONE $(distdir)/doc $(distdir)/driver $(distdir)/intrinsic.lib $(distdir)/mdes/Limpact $(distdir)/mdes/Ltahoe $(distdir)/mdes/structure $(distdir)/parms $(distdir)/platform $(distdir)/platform/hp_cc $(distdir)/platform/hp_cc/include $(distdir)/platform/ia64lin_gcc $(distdir)/platform/x86lin_gcc $(distdir)/platform/x86lin_gcc/include/_newgcc $(distdir)/platform/x86lin_gcc/include/bits $(distdir)/projects/full $(distdir)/scripts $(distdir)/src $(distdir)/src/Lcode/Lcode $(distdir)/src/Lcode/codegen/Limpact $(distdir)/src/Lcode/codegen/Lschedule $(distdir)/src/Lcode/codegen/Lsoftpipe $(distdir)/src/Lcode/codegen/Ltahoe $(distdir)/src/Lcode/codegen/Mopti $(distdir)/src/Lcode/codegen/Mopti-ia64 $(distdir)/src/Lcode/codegen/Regalloc $(distdir)/src/Lcode/opti/Lblock $(distdir)/src/Lcode/opti/Lmarkpipe $(distdir)/src/Lcode/opti/Lopti $(distdir)/src/Lcode/opti/Lsafe $(distdir)/src/Lcode/opti/Lsuperscalar $(distdir)/src/Lcode/performance/Lencode $(distdir)/src/Lcode/performance/Lget $(distdir)/src/Lcode/performance/Lprobe $(distdir)/src/Lcode/performance/Lprofile $(distdir)/src/Lcode/sched/SM $(distdir)/src/Lcode/tools/Lbuild_prototype_info $(distdir)/src/Lcode/tools/Lemulate $(distdir)/src/Lcode/tools/Lgp_rel $(distdir)/src/Lcode/tools/Linduct $(distdir)/src/Lcode/tools/Lsplit $(distdir)/src/Lcode/tools/Lsplit_cbs $(distdir)/src/Lcode/tools/Lstatic $(distdir)/src/Pcode/Pannotate $(distdir)/src/Pcode/Pcode $(distdir)/src/Pcode/Pflatten $(distdir)/src/Pcode/Pinline $(distdir)/src/Pcode/Pipa $(distdir)/src/Pcode/Plib_CF $(distdir)/src/Pcode/Plib_DD $(distdir)/src/Pcode/Plib_SS $(distdir)/src/Pcode/Plib_probe $(distdir)/src/Pcode/Plink $(distdir)/src/Pcode/Pmerge_iter $(distdir)/src/Pcode/Pmerge_prof $(distdir)/src/Pcode/Pomega $(distdir)/src/Pcode/Protate $(distdir)/src/Pcode/Psymtab $(distdir)/src/Pcode/PtoC $(distdir)/src/Pcode/PtoL $(distdir)/src/Pcode/PtoNM $(distdir)/src/bdd $(distdir)/src/library $(distdir)/src/machine/Lmdes $(distdir)/src/machine/Lmdes_build $(distdir)/src/machine/Mspec $(distdir)/src/machine/convert_hmdes $(distdir)/src/machine/hmdes $(distdir)/src/machine/lmdes2_customizer $(distdir)/src/machine/md_compiler $(distdir)/src/machine/md_preprocessor
 	@srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; \
 	topsrcdirstrip=`echo "$(top_srcdir)" | sed 's|.|.|g'`; \
 	list='$(DISTFILES)'; for file in $$list; do \
@@ -20901,7 +21039,7 @@
 all-am: Makefile $(LIBRARIES) $(PROGRAMS) $(SCRIPTS) $(DATA) $(HEADERS)
 
 installdirs:
-	$(mkinstalldirs) $(DESTDIR)$(libdir) $(DESTDIR)$(bindir) $(DESTDIR)$(bindir) $(DESTDIR)$(driverdir) $(DESTDIR)$(platform_hp_ccdir) $(DESTDIR)$(scriptsdir) $(DESTDIR)$(benchmarks_NONEdir) $(DESTDIR)$(driverdir) $(DESTDIR)$(intrinsic_libdir) $(DESTDIR)$(mdes_Ltahoedir) $(DESTDIR)$(mdes_structuredir) $(DESTDIR)$(parmsdir) $(DESTDIR)$(platform_hp_ccdir) $(DESTDIR)$(platform_hp_cc_includedir) $(DESTDIR)$(platform_ia64lin_gccdir) $(DESTDIR)$(platform_ia64lin_gcc_includedir) $(DESTDIR)$(platform_x86lin_gccdir) $(DESTDIR)$(platform_x86lin_gcc_includedir) $(DESTDIR)$(platform_x86lin_gcc_include__newgccdir) $(DESTDIR)$(platform_x86lin_gcc_include_bitsdir) $(DESTDIR)$(projects_fulldir) $(DESTDIR)$(intrinsic_libdir) $(DESTDIR)$(mdes_Ltahoedir) $(DESTDIR)$(mdes_structuredir) $(DESTDIR)$(platform_hp_ccdir) $(DESTDIR)$(platform_ia64lin_gccdir) $(DESTDIR)$(platform_ia64lin_gcc_IPA_libdir) $(DESTDIR)$(platform_x86lin_gccdir) $(DESTDIR)$(platform_x86lin_gcc_IPA_libdir) $(DESTDIR)$(src_Lcode_performance_Lprobedir) $(DESTDIR)$(src_librarydir)
+	$(mkinstalldirs) $(DESTDIR)$(libdir) $(DESTDIR)$(bindir) $(DESTDIR)$(bindir) $(DESTDIR)$(driverdir) $(DESTDIR)$(platform_hp_ccdir) $(DESTDIR)$(scriptsdir) $(DESTDIR)$(benchmarks_NONEdir) $(DESTDIR)$(driverdir) $(DESTDIR)$(intrinsic_libdir) $(DESTDIR)$(mdes_Limpactdir) $(DESTDIR)$(mdes_Ltahoedir) $(DESTDIR)$(mdes_structuredir) $(DESTDIR)$(parmsdir) $(DESTDIR)$(platform_hp_ccdir) $(DESTDIR)$(platform_hp_cc_includedir) $(DESTDIR)$(platform_ia64lin_gccdir) $(DESTDIR)$(platform_ia64lin_gcc_includedir) $(DESTDIR)$(platform_x86lin_gccdir) $(DESTDIR)$(platform_x86lin_gcc_includedir) $(DESTDIR)$(platform_x86lin_gcc_include__newgccdir) $(DESTDIR)$(platform_x86lin_gcc_include_bitsdir) $(DESTDIR)$(projects_fulldir) $(DESTDIR)$(intrinsic_libdir) $(DESTDIR)$(mdes_Limpactdir) $(DESTDIR)$(mdes_Ltahoedir) $(DESTDIR)$(mdes_structuredir) $(DESTDIR)$(platform_hp_ccdir) $(DESTDIR)$(platform_ia64lin_gccdir) $(DESTDIR)$(platform_ia64lin_gcc_IPA_libdir) $(DESTDIR)$(platform_x86lin_gccdir) $(DESTDIR)$(platform_x86lin_gcc_IPA_libdir) $(DESTDIR)$(src_Lcode_performance_Lprobedir) $(DESTDIR)$(src_librarydir)
 
 install: install-am
 install-exec: install-exec-am
@@ -21122,8 +21260,9 @@
 
 install-data-am: install-dist_benchmarks_NONEDATA \
 	install-dist_driverDATA install-dist_intrinsic_libDATA \
-	install-dist_mdes_LtahoeDATA install-dist_mdes_structureDATA \
-	install-dist_parmsDATA install-dist_platform_hp_ccDATA \
+	install-dist_mdes_LimpactDATA install-dist_mdes_LtahoeDATA \
+	install-dist_mdes_structureDATA install-dist_parmsDATA \
+	install-dist_platform_hp_ccDATA \
 	install-dist_platform_hp_cc_includeDATA \
 	install-dist_platform_ia64lin_gccDATA \
 	install-dist_platform_ia64lin_gcc_includeDATA \
@@ -21132,8 +21271,8 @@
 	install-dist_platform_x86lin_gcc_include__newgccDATA \
 	install-dist_platform_x86lin_gcc_include_bitsDATA \
 	install-dist_projects_fullDATA install-driverSCRIPTS \
-	install-intrinsic_libDATA install-mdes_LtahoeDATA \
-	install-mdes_structureDATA \
+	install-intrinsic_libDATA install-mdes_LimpactDATA \
+	install-mdes_LtahoeDATA install-mdes_structureDATA \
 	install-nodist_src_Lcode_performance_LprobeHEADERS \
 	install-nodist_src_libraryHEADERS install-platform_hp_ccDATA \
 	install-platform_hp_ccSCRIPTS install-platform_ia64lin_gccDATA \
@@ -21171,7 +21310,8 @@
 
 uninstall-am: uninstall-binPROGRAMS uninstall-binSCRIPTS \
 	uninstall-dist_benchmarks_NONEDATA uninstall-dist_driverDATA \
-	uninstall-dist_intrinsic_libDATA uninstall-dist_mdes_LtahoeDATA \
+	uninstall-dist_intrinsic_libDATA \
+	uninstall-dist_mdes_LimpactDATA uninstall-dist_mdes_LtahoeDATA \
 	uninstall-dist_mdes_structureDATA uninstall-dist_parmsDATA \
 	uninstall-dist_platform_hp_ccDATA \
 	uninstall-dist_platform_hp_cc_includeDATA \
@@ -21183,8 +21323,8 @@
 	uninstall-dist_platform_x86lin_gcc_include_bitsDATA \
 	uninstall-dist_projects_fullDATA uninstall-driverSCRIPTS \
 	uninstall-info-am uninstall-intrinsic_libDATA \
-	uninstall-libLIBRARIES uninstall-mdes_LtahoeDATA \
-	uninstall-mdes_structureDATA \
+	uninstall-libLIBRARIES uninstall-mdes_LimpactDATA \
+	uninstall-mdes_LtahoeDATA uninstall-mdes_structureDATA \
 	uninstall-nodist_src_Lcode_performance_LprobeHEADERS \
 	uninstall-nodist_src_libraryHEADERS \
 	uninstall-platform_hp_ccDATA uninstall-platform_hp_ccSCRIPTS \
@@ -21202,8 +21342,9 @@
 	install-am install-binPROGRAMS install-binSCRIPTS install-data \
 	install-data-am install-dist_benchmarks_NONEDATA \
 	install-dist_driverDATA install-dist_intrinsic_libDATA \
-	install-dist_mdes_LtahoeDATA install-dist_mdes_structureDATA \
-	install-dist_parmsDATA install-dist_platform_hp_ccDATA \
+	install-dist_mdes_LimpactDATA install-dist_mdes_LtahoeDATA \
+	install-dist_mdes_structureDATA install-dist_parmsDATA \
+	install-dist_platform_hp_ccDATA \
 	install-dist_platform_hp_cc_includeDATA \
 	install-dist_platform_ia64lin_gccDATA \
 	install-dist_platform_ia64lin_gcc_includeDATA \
@@ -21214,7 +21355,8 @@
 	install-dist_projects_fullDATA install-driverSCRIPTS \
 	install-exec install-exec-am install-info install-info-am \
 	install-intrinsic_libDATA install-libLIBRARIES install-man \
-	install-mdes_LtahoeDATA install-mdes_structureDATA \
+	install-mdes_LimpactDATA install-mdes_LtahoeDATA \
+	install-mdes_structureDATA \
 	install-nodist_src_Lcode_performance_LprobeHEADERS \
 	install-nodist_src_libraryHEADERS install-platform_hp_ccDATA \
 	install-platform_hp_ccSCRIPTS install-platform_ia64lin_gccDATA \
@@ -21227,7 +21369,7 @@
 	tags uninstall uninstall-am uninstall-binPROGRAMS \
 	uninstall-binSCRIPTS uninstall-dist_benchmarks_NONEDATA \
 	uninstall-dist_driverDATA uninstall-dist_intrinsic_libDATA \
-	uninstall-dist_mdes_LtahoeDATA \
+	uninstall-dist_mdes_LimpactDATA uninstall-dist_mdes_LtahoeDATA \
 	uninstall-dist_mdes_structureDATA uninstall-dist_parmsDATA \
 	uninstall-dist_platform_hp_ccDATA \
 	uninstall-dist_platform_hp_cc_includeDATA \
@@ -21239,8 +21381,8 @@
 	uninstall-dist_platform_x86lin_gcc_include_bitsDATA \
 	uninstall-dist_projects_fullDATA uninstall-driverSCRIPTS \
 	uninstall-info-am uninstall-intrinsic_libDATA \
-	uninstall-libLIBRARIES uninstall-mdes_LtahoeDATA \
-	uninstall-mdes_structureDATA \
+	uninstall-libLIBRARIES uninstall-mdes_LimpactDATA \
+	uninstall-mdes_LtahoeDATA uninstall-mdes_structureDATA \
 	uninstall-nodist_src_Lcode_performance_LprobeHEADERS \
 	uninstall-nodist_src_libraryHEADERS \
 	uninstall-platform_hp_ccDATA uninstall-platform_hp_ccSCRIPTS \
@@ -22833,6 +22975,1249 @@
 		bin/md_preprocessor $(abs_srcdir)/$(file) | \
 		bin/md_compiler -stdin -o $${output};)
 
+mdes/Limpact mdes/Limpact/: $(mdes_Limpact_DATA)
+
+mdes/Limpact/clean:
+	rm -f $(mdes_Limpact_CLN)
+
+mdes/Limpact/EPIC_1G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_1G_1BL.lmdes2 -DWIDTH=1 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_2G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_2G_1BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_2G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_2G_2BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_4G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_4G_1BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_4G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_4G_2BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_4G_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_4G_4BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_8G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_1BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_8G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_2BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_8G_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_4BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_8G_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_8BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+# Build separate TI `C6x-based EPIC MIX    MCM 2/2000
+mdes/Limpact/EPIC_8G_1BL_TI.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/EPIC_8G_1BL_TI.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/EPIC_8G_1BL_TI.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_1BL_TI.lmdes2 -DWIDTH=8
+
+# Build Itanium-like EPIC MIX MCM 3/2001
+mdes/Limpact/EPIC_8G_MIX_3BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_MIX_3BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=3 -DNUM_IALUS=5 -DNUM_FALUS=3 -DNUM_DIVS=1 \
+		-DNUM_MEM_UNITS=3 -DNUM_CHK=8 -DBRANCHES_AT_END=0 \
+		-DNON_TRAPPING_OPS=1 -DLOAD_LAT=2
+
+# Build Itanium-like EPIC MIX MCM 3/2001
+mdes/Limpact/EPIC_8G_MIX_3BX_LDLAT3.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_MIX_3BX_LDLAT3.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=3 -DNUM_IALUS=5 -DNUM_FALUS=3 -DNUM_DIVS=1 \
+		-DNUM_MEM_UNITS=3 -DNUM_CHK=8 -DBRANCHES_AT_END=0 \
+		-DNON_TRAPPING_OPS=1 -DLOAD_LAT=3
+
+mdes/Limpact/EPIC_16G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16G_1BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_16G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16G_2BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_16G_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16G_4BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_16G_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16G_8BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_16G_16BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16G_16BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=16 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_1R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_1R_1BL.lmdes2 -DWIDTH=1 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_2R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_2R_1BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_2R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_2R_2BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_4R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_4R_1BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_4R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_4R_2BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_4R_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_4R_4BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_8R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8R_1BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_8R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8R_2BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_8R_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8R_4BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_8R_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8R_8BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_16R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16R_1BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_16R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16R_2BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_16R_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16R_4BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_16R_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16R_8BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_16R_16BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16R_16BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=16 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+# WARNING - ISSUE rates and BRANCH rates are zero relative!!!!
+# general percolation models
+mdes/Limpact/IMPACT_1G.lmdes mdes/Limpact/IMPACT_1G.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_1G.lmdes -DISSUE=0 -DBRANCH=0
+
+mdes/Limpact/IMPACT_2G_1BR.lmdes mdes/Limpact/IMPACT_2G_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_2G_1BR.lmdes -DISSUE=1 -DBRANCH=0
+
+mdes/Limpact/IMPACT_2G.lmdes mdes/Limpact/IMPACT_2G.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_2G.lmdes -DISSUE=1 -DBRANCH=1
+
+mdes/Limpact/IMPACT_3G_1BR.lmdes mdes/Limpact/IMPACT_3G_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_3G_1BR.lmdes -DISSUE=2 -DBRANCH=0
+
+mdes/Limpact/IMPACT_3G_2BR.lmdes mdes/Limpact/IMPACT_3G_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_3G_2BR.lmdes -DISSUE=2 -DBRANCH=1
+
+mdes/Limpact/IMPACT_3G.lmdes mdes/Limpact/IMPACT_3G.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_3G.lmdes -DISSUE=2 -DBRANCH=2
+
+mdes/Limpact/IMPACT_4G_1BR.lmdes mdes/Limpact/IMPACT_4G_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_4G_1BR.lmdes -DISSUE=3 -DBRANCH=0
+
+mdes/Limpact/IMPACT_4G_2BR.lmdes mdes/Limpact/IMPACT_4G_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_4G_2BR.lmdes -DISSUE=3 -DBRANCH=1
+
+mdes/Limpact/IMPACT_4G.lmdes mdes/Limpact/IMPACT_4G.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_4G.lmdes -DISSUE=3 -DBRANCH=3
+
+mdes/Limpact/IMPACT_8G_1BR.lmdes mdes/Limpact/IMPACT_8G_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_8G_1BR.lmdes -DISSUE=7 -DBRANCH=0
+
+mdes/Limpact/IMPACT_8G_2BR.lmdes mdes/Limpact/IMPACT_8G_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_8G_2BR.lmdes -DISSUE=7 -DBRANCH=1
+
+mdes/Limpact/IMPACT_8G_4BR.lmdes mdes/Limpact/IMPACT_8G_4BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_8G_4BR.lmdes -DISSUE=7 -DBRANCH=3
+
+mdes/Limpact/IMPACT_8G.lmdes mdes/Limpact/IMPACT_8G.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_8G.lmdes -DISSUE=7 -DBRANCH=7
+
+mdes/Limpact/IMPACT_16G_1BR.lmdes mdes/Limpact/IMPACT_16G_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_16G_1BR.lmdes -DISSUE=15 -DBRANCH=0
+
+mdes/Limpact/IMPACT_16G_2BR.lmdes mdes/Limpact/IMPACT_16G_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_16G_2BR.lmdes -DISSUE=15 -DBRANCH=1
+
+mdes/Limpact/IMPACT_16G_4BR.lmdes mdes/Limpact/IMPACT_16G_4BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_16G_4BR.lmdes -DISSUE=15 -DBRANCH=3
+
+mdes/Limpact/IMPACT_16G_8BR.lmdes mdes/Limpact/IMPACT_16G_8BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_16G_8BR.lmdes -DISSUE=15 -DBRANCH=7
+
+mdes/Limpact/IMPACT_16G.lmdes mdes/Limpact/IMPACT_16G.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_16G.lmdes -DISSUE=15 -DBRANCH=15
+
+# restricted percolation models
+mdes/Limpact/IMPACT_1R.lmdes mdes/Limpact/IMPACT_1R.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_1R.lmdes -DISSUE=0 -DBRANCH=0
+
+mdes/Limpact/IMPACT_2R_1BR.lmdes mdes/Limpact/IMPACT_2R_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_2R_1BR.lmdes -DISSUE=1 -DBRANCH=0
+
+mdes/Limpact/IMPACT_2R.lmdes mdes/Limpact/IMPACT_2R.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_2R.lmdes -DISSUE=1 -DBRANCH=1
+
+mdes/Limpact/IMPACT_4R_1BR.lmdes mdes/Limpact/IMPACT_4R_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_4R_1BR.lmdes -DISSUE=3 -DBRANCH=0
+
+mdes/Limpact/IMPACT_4R_2BR.lmdes mdes/Limpact/IMPACT_4R_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_4R_2BR.lmdes -DISSUE=3 -DBRANCH=1
+
+mdes/Limpact/IMPACT_4R.lmdes mdes/Limpact/IMPACT_4R.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_4R.lmdes -DISSUE=3 -DBRANCH=3
+
+mdes/Limpact/IMPACT_8R_1BR.lmdes mdes/Limpact/IMPACT_8R_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_8R_1BR.lmdes -DISSUE=7 -DBRANCH=0
+
+mdes/Limpact/IMPACT_8R_2BR.lmdes mdes/Limpact/IMPACT_8R_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_8R_2BR.lmdes -DISSUE=7 -DBRANCH=1
+
+mdes/Limpact/IMPACT_8R_4BR.lmdes mdes/Limpact/IMPACT_8R_4BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_8R_4BR.lmdes -DISSUE=7 -DBRANCH=3
+
+mdes/Limpact/IMPACT_8R.lmdes mdes/Limpact/IMPACT_8R.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_8R.lmdes -DISSUE=7 -DBRANCH=7
+
+mdes/Limpact/IMPACT_16R_1BR.lmdes mdes/Limpact/IMPACT_16R_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_16R_1BR.lmdes -DISSUE=15 -DBRANCH=0
+
+mdes/Limpact/IMPACT_16R_2BR.lmdes mdes/Limpact/IMPACT_16R_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_16R_2BR.lmdes -DISSUE=15 -DBRANCH=1
+
+mdes/Limpact/IMPACT_16R_4BR.lmdes mdes/Limpact/IMPACT_16R_4BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_16R_4BR.lmdes -DISSUE=15 -DBRANCH=3
+
+mdes/Limpact/IMPACT_16R_8BR.lmdes mdes/Limpact/IMPACT_16R_8BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_16R_8BR.lmdes -DISSUE=15 -DBRANCH=7
+
+mdes/Limpact/IMPACT_16R.lmdes mdes/Limpact/IMPACT_16R.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_16R.lmdes -DISSUE=15 -DBRANCH=15
+
+mdes/Limpact/SS_1G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_1G_1BL.lmdes2 -DWIDTH=1 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_1G_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_1G_1BX.lmdes2 -DWIDTH=1 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_2G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2G_1BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_2G_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2G_1BX.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_2G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2G_2BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_2G_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2G_2BX.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_4G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4G_1BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_4G_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4G_1BX.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_4G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4G_2BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_4G_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4G_2BX.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_4G_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4G_4BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_4G_4BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4G_4BX.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_1BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_1BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_2BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_2BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_4BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_4BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_4BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_8BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_8BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_8BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_1BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_1BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_2BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_2BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_4BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_4BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_4BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_8BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_8BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_8BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_16BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_16BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=16 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_16BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_16BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=16 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_1R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_1R_1BL.lmdes2 -DWIDTH=1 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_1R_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_1R_1BX.lmdes2 -DWIDTH=1 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_2R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2R_1BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_2R_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2R_1BX.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_2R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2R_2BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_2R_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2R_2BX.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_4R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4R_1BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_4R_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4R_1BX.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_4R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4R_2BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_4R_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4R_2BX.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_4R_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4R_4BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_4R_4BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4R_4BX.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_1BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_1BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_2BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_2BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_4BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_4BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_4BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_8BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_8BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_8BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_1BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_1BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_2BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_2BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_4BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_4BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_4BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_8BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_8BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_8BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_16BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_16BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=16 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_16BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_16BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=16 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
 mdes/Ltahoe mdes/Ltahoe/: $(mdes_Ltahoe_DATA)
 
 mdes/Ltahoe/clean:
@@ -22867,7 +24252,7 @@
 	mdes/structure mdes/Limpact mdes/Ltahoe mdes/Lstarcore
 
 mdes/clean:
-	mdes/structure/clean  mdes/Ltahoe/clean 
+	mdes/structure/clean mdes/Limpact/clean mdes/Ltahoe/clean 
 
 @HOST_PLATFORM_HP_CC_TRUE@@TARGET_PLATFORM_HP_CC_TRUE@platform/hp_cc platform/hp_cc/: $(platform_hp_cc_LIB)
 
diff -urN openimpact-1.0rc4/mdes/Limpact/EPIC_8G_1BL_TI.hmdes2 openimpact-1.0rc4.Limpact/mdes/Limpact/EPIC_8G_1BL_TI.hmdes2
--- openimpact-1.0rc4/mdes/Limpact/EPIC_8G_1BL_TI.hmdes2	1969-12-31 18:00:00.000000000 -0600
+++ openimpact-1.0rc4.Limpact/mdes/Limpact/EPIC_8G_1BL_TI.hmdes2	2004-09-17 14:41:02.000000000 -0500
@@ -0,0 +1,882 @@
+/*****************************************************************************\
+ *
+ *		      Illinois Open Source License
+ *                     University of Illinois/NCSA
+ *                         Open Source License
+ *
+ * Copyright (c) 2004, The University of Illinois at Urbana-Champaign.
+ * All rights reserved.
+ *
+ * Developed by:             
+ *
+ *		IMPACT Research Group
+ *
+ *		University of Illinois at Urbana-Champaign
+ *
+ *              http://www.crhc.uiuc.edu/IMPACT
+ *              http://www.gelato.org
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal with the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimers.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimers in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the names of the IMPACT Research Group, the University of
+ * Illinois, nor the names of its contributors may be used to endorse
+ * or promote products derived from this Software without specific
+ * prior written permission.  THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
+ * LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+ * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS WITH THE SOFTWARE.
+ *
+\*****************************************************************************/
+/*****************************************************************************\
+ *
+ *  File:  IMPACT_SIMPLE_TEMPLATE.hmdes2
+ *
+ *  Description:  Simple machine description template for wide-variety of 
+ *                experimental processors that execute IMPACT's Lcode.
+ *                This simplified template does not model register ports and
+ *                uses a fairly simple function unit model.  It is designed
+ *                to be relatively easy to understand and modify.  
+ * 
+ *  Note: For hmdes2 documentation (slightly out-of-date), see:
+ * 
+ *          HMDES Version 2 Specification 
+ *          John C. Gyllenhaal, Wen-mei W. Hwu and B. Ramakrishna Rau
+ *          IMPACT Technical report, IMPACT-96-03, 
+ *          University of Illinois, Urbana IL. 1996.
+ *          http://www.crhc.uiuc.edu/IMPACT/ftp/report/impact-96-03.hmdes2.pdf
+ *
+ *  Note: Although IMPACT's and HPL's (Elcor) machine descriptions share a 
+ *        common host language "MD" (aka as "dabble" at HPL), they are not 
+ *        currently compatible with each other.  This machine description 
+ *        cannot be used with Trimaran's Elcor-based scheduler and Elcor's
+ *        machine descriptions cannot be used with IMPACT-based schedulers.
+ *        
+ *  Creation Date :  June 1999
+ *
+ *  Author:  John C. Gyllenhaal, Wen-mei Hwu
+ *
+ *  Revisions:
+ *
+\*****************************************************************************/
+
+/* Read in the IMPACT's expected structure for this .hmdes2 file */
+$include "${IMPACT_REL_PATH}/mdes/structure/structure_IMPACT.hmdes2"
+
+/*
+ * Cycle in which UBR / CBR load source predicate.  Setting to 1 instead
+ * of 0 yields a 0-cycle-delay between pred defines and branches.
+ */
+$def PBDELAY            0
+
+/* 
+ * Scheduling 'slots' are used by the scheduler to determine ordering of 
+ * operations within an operation packet (operations scheduled to execute 
+ * in the same cycle).  The 'decoder' resources are used by this machine
+ * description to set the maximum number of operations that can be issued 
+ * per cycle (WIDTH).  The 'branch' resources are used by this
+ * machine description to set the maximum number of branches that can
+ * be issued per cycle (NUM_BRANCHES).
+ *
+ * If there are no constraints on operation ordering within the packet
+ * (i.e., branches can be scheduled anywhere), we will create the same
+ * number of slots as decoders.  
+ *
+ *   Example SS_3G_2BX (3-issue, 2 branches anywhere):
+ *          slot0: any operation (branch or non-branch)
+ *          slot1: any operation 
+ *          slot2: any operation 
+ *       decoder1: any operation
+ *       decoder2: any operation
+ *       decoder3: any operation
+ *        branch1: any branch
+ *        branch2: any branch
+ *
+ *
+ * If branches must be placed at the end, but there is only one branch,
+ * we still create the same number of slots as decoders and just
+ * require branches to use the last slot.
+ *
+ *   Example SS_3G_1BL (3-issue, 1 branch last):
+ *          slot0: non-branch operation 
+ *          slot1: non-branch operation 
+ *          slot2: any operation 
+ *       decoder1: any operation
+ *       decoder2: any operation
+ *       decoder3: any operation
+ *        branch1: any branch
+ *
+ * If branches must be placed at the end, but there are more than one branch,
+ * we need to create more slots than decoders, in order to force branches
+ * to the end.  Although there are more slots in this case, the decoders
+ * still limit the operations per cycle (to WIDTH).
+ *
+ *   Example SS_3G_2BL (3-issue, 2 branches last):
+ *          slot0: non-branch operation   <- add1
+ *          slot1: non-branch operation   <- (not used)
+ *          slot2: any operation          <- branch1
+ *          slot3: branch operation       <- branch2
+ *       decoder1: any operation          <- add1
+ *       decoder2: any operation          <- branch1
+ *       decoder3: any operation          <- branch2
+ *        branch1: any branch             <- branch1
+ *        branch2: any branch             <- branch2
+ *
+ *  Example of why using the same number of slots does not work for SS_3G_2BL:
+ *          slot0: non-branch operation   <- add1
+ *          slot1: any operation          <- branch1
+ *          slot2: any operation          <- add2    (*not allowed*)
+ *       decoder1: any operation          <- add1
+ *       decoder2: any operation          <- branch1
+ *       decoder3: any operation          <- add2
+ *        branch1: any branch             <- branch1
+ *        branch2: any branch             <- (not used)
+ * 
+ * In the SS_3G_2BL example, it is *still* a three issue processor even
+ * though it has four issue slots!
+ *
+ * For historical reasons, the scheduler tools expect the slots to be
+ * numbered slot0,...slotN.
+ */
+
+    /* Create the minimum number of slots that allow us to force
+     * branches to the end of the operation packet.
+     */
+    $def LAST_SLOT $={7}
+    $def WIDTH $={8}
+
+/* Section for passing parameters to IMPACT's scheduler and 
+ * lmdes2_customizer 
+ */
+SECTION Parameter
+{
+  /* Used by lmdes2_customizer to assign integer numbers to many of the
+   * strings in this machine description, such as Lop_ADD, Label, REG
+   * EXCEPT, LOAD, etc.
+   */
+  customization_headers
+                (value("${IMPACT_ROOT}/include/Lcode/l_opc.h"
+                       "${IMPACT_ROOT}/include/Lcode/l_flags.h"
+                       "${IMPACT_ROOT}/include/Lcode/limpact_phase1.h"
+                       "${IMPACT_ROOT}/include/machine/m_spec.h"
+                       "${IMPACT_ROOT}/include/machine/m_impact.h"));
+
+  /* Phased out in version 2.31, but should always be set to "superscalar" 
+   * for backward compatibilty and so lmdes2_customizer does not complain.
+   * It is OK to set this to superscalar when targeting an EPIC processor!
+   */
+  processor_model (value("superscalar"));
+
+}
+
+/* Convert the scheduler operand types (NULL, p, i, f, f2, Label, and Lit)
+ * into the short name (A) that will be used to describe 
+ * the operation format mapping entries in Operation_Format.
+ */
+SECTION Field_Type
+{
+  /* Names the scheduler (thru Mspec) will use to describe the operands */
+  NULL ();                              // No operand allowed
+  p ();                                 // Predicate register operand 
+  i ();                                 // Integer register operand 
+  f ();                                 // Float register operand 
+  f2 ();                                // Double register operand 
+  Label ();                             // Generic label literal
+  Lit ();			        // Generic non-label literal
+  REG (compatible_with (i f f2));      // Generic register operand
+
+  /* Remap and group the names above into one letter names for ease of use 
+   * below in Operation Format.  Since not modeling register port usage
+   * in this template, just map everything to 'A'.
+   */
+  A (compatible_with (NULL p i f f2 Label Lit REG)); // Anything allowed
+}
+
+/* Define all the operation formats supported in the target machine.
+ *
+ * All entrys are in the form:
+ *   P0_D0D1_S0S1S2  
+ *
+ * where:
+ *   P0       is the pred[0] operand specifier 
+ *   D0       is the dest[0] operand specifier 
+ *   D1       is the dest[1] operand specifier 
+ *   S0       is the src[0] operand specifier 
+ *   S1       is the src[1] operand specifier 
+ *   S2       is the src[2] operand specifier 
+ *   
+ * Since in this template, we are not modeling register port usage, only
+ * one operation format is needed (significantly simplifying the rest of
+ * the machine description).
+ */
+SECTION Operation_Format
+{
+  A_AAAA_AAAAAA                       (pred (A) dest (A A A A) src (A A A A A A));
+}
+
+
+/*
+ *  Declare the processor resources that we wish to model.
+ *
+ *  Note: The resource names (such as decoder1) are *not* keywords.
+ *        Renaming all the resources to r1, r2, r3... r30 (and 
+ *        their references) will yield the exact same schedule.
+ *
+ *  Note: You can use as many or few resources as desired in order
+ *        to model the processor's execution constraints.  Typically,
+ *        we don't model anything that doesn't add execution constraints
+ *        (e.g., pipeline stages in fully-pipelined function units, etc.).
+ *         
+ *
+ *  Note: The 'slot' field is used to associate slot ids with particular
+ *        resource names.  For simplicity, we assign slot id 0, to slot0,
+ *        etc.  Not defining the 'slot' field indicates that this is 
+ *        a non-slot (i.e., normal) resource.
+ *        For example, to associate scheduler slot 3, with resource 
+ *        'my_slot_3':
+ *           my_slot_3 (slot(3));
+ */
+SECTION Resource
+{
+  /* Slots are used to control how operations are scheduled within the
+   * same cycle (instruction packet).  For historical reasons, slots
+   * are numbered starting from 0 (the first slot in the packet).
+   */
+  $for (I in $0..${LAST_SLOT})
+  {
+      slot${I} (slot(${I}));
+  }
+
+  /* Decoders are used to limit the number of operations that can
+   * issue in one cycle.
+   */
+  $for (I in $1..${WIDTH})
+  {
+      decoder${I} ();
+  }
+
+  /* Create the various functional units for this machine
+   * Note: All these units are assumed to be fully pipelined, so
+   *       we only need to model the first stage.
+   */
+  Lunit1 ();
+  Lunit2 ();
+  Munit1 ();
+  Munit2 ();
+  Dunit1 ();
+  Dunit2 ();
+  Sunit1 ();
+  Sunit2 ();
+
+}
+
+/*
+ * Specify the possible times in the pipeline the resources can be 
+ * used.  Here is the time mapping used in this machine description
+ * for resource usages:
+ * 
+ *   0 -> Fetch stage
+ *   1 -> Decode stage
+ *   2 -> First execution stage
+ *   3 -> Second execution stage and write-back stage for latency 1 ops
+ *   4 -> Third execution stage and write-back stage for latency 2 ops
+ *   etc.
+ */
+SECTION Resource_Usage
+{
+
+  /*
+   * Fetch stage
+   */    
+  $for (I in $0..${LAST_SLOT})
+  {
+      RU_slot${I}_t0_0 (use(slot${I}) time (0));
+  }
+
+
+  /*
+   * Decoder stage
+   */
+  $for (I in $1..${WIDTH})
+  {
+      RU_decoder${I}_t1_1 (use(decoder${I}) time (1));
+  }
+
+
+  /*
+   * First execution stage
+   */
+  RU_Lunit1_t2_2 (use(Lunit1) time (2));
+  RU_Lunit2_t2_2 (use(Lunit2) time (2));
+  RU_Munit1_t2_2 (use(Munit1) time (2));
+  RU_Munit2_t2_2 (use(Munit2) time (2));
+  RU_Dunit1_t2_2 (use(Dunit1) time (2));
+  RU_Dunit2_t2_2 (use(Dunit2) time (2));
+  RU_Sunit1_t2_2 (use(Sunit1) time (2));
+  RU_Sunit2_t2_2 (use(Sunit2) time (2));
+
+  /*
+   * Second execution stage and write-back stage for latency 1 ops
+   * etc.
+   */
+  /*
+   * We are assuming fully-pipelined functional units, so later
+   * stages do not need to be modeled.  We are not modeling register
+   * ports, so the write-backs don't need to be modeled.
+   */
+}
+
+/* Group together resource usages that should always be used together.
+ * None necessary for this simplified machine description.
+ */
+SECTION Resource_Unit
+{ 
+}
+
+/* Create options where any one of the options may be selected.
+ * For example, any one of the declared IALUs may be used.
+ *
+ * Note: Table options are used to create the OR part of AND/OR-trees.
+ */
+SECTION Table_Option
+{
+  /* Use any "normal" slot for non-branch operations. */
+  any_normal_slot_t0_0 
+  (
+      one_of($for (I in $0..(${WIDTH}-1)) {RU_slot${I}_t0_0 })
+  );
+
+  /* If placing branches at end, branches can only use the last normal
+   * slot and the extra slots after the normal slots (if 2 or more branches).
+   */
+  any_branch_slot_t0_0
+  (
+      one_of($for (I in $(${WIDTH}-1)..${LAST_SLOT}){RU_slot${I}_t0_0 })
+  );
+
+  /* 
+   * Allow any of the decoders to be used. 
+   * This resource use limits the processor's issue width, not slots.
+   */
+  any_decoder_t1_1 
+  (
+      one_of($for (I in $1..${WIDTH}){RU_decoder${I}_t1_1 })
+  );
+
+  /* 
+   * Allow the various types of instructions to execute on the
+   *  specified functional units.
+   */
+  arith_t2_2 
+  (
+      one_of( RU_Lunit1_t2_2 RU_Lunit2_t2_2 RU_Dunit1_t2_2 RU_Dunit2_t2_2 RU_Sunit1_t2_2 RU_Sunit2_t2_2 )
+  );
+
+  multdiv_t2_2 
+  (
+      one_of( RU_Munit1_t2_2 RU_Munit2_t2_2 )
+  );
+
+  logic_t2_2 
+  (
+      one_of( RU_Lunit1_t2_2 RU_Lunit2_t2_2 RU_Sunit1_t2_2 RU_Sunit2_t2_2 )
+  );
+
+  farith_t2_2 
+  (
+      one_of( RU_Lunit1_t2_2 RU_Lunit2_t2_2 RU_Sunit1_t2_2 RU_Sunit2_t2_2 )
+  );
+
+  fmultdiv_t2_2 
+  (
+      one_of( RU_Munit1_t2_2 RU_Munit2_t2_2 )
+  );
+
+  frecsqrt_t2_2 
+  (
+      one_of( RU_Sunit1_t2_2 RU_Sunit2_t2_2 )
+  );
+
+  fconv_t2_2 
+  (
+      one_of( RU_Lunit1_t2_2 RU_Lunit2_t2_2 )
+  );
+
+  branch_t2_2 
+  (
+      one_of( RU_Sunit2_t2_2 )
+  );
+
+  shiftbit_t2_2 
+  (
+      one_of( RU_Sunit1_t2_2 RU_Sunit2_t2_2 )
+  );
+
+  mem_t2_2 
+  (
+      one_of( RU_Dunit1_t2_2 RU_Dunit2_t2_2 )
+  );
+
+  nop_t2_2 
+  (
+      one_of( RU_Lunit1_t2_2 RU_Lunit2_t2_2 RU_Dunit1_t2_2 RU_Dunit2_t2_2 RU_Munit1_t2_2 RU_Munit2_t2_2 RU_Sunit1_t2_2 RU_Sunit2_t2_2 )
+  );
+
+}
+
+/* Create the AND-OR trees that describes the how the processor resources
+ * are used as the operation executes.  This is the AND part of the
+ * AND/OR-tree representation for reservation tables.
+ *
+ * Any mixture of Table_Option, Resource_Unit, and Resource Usage entries
+ * may be specified in the 'use' field.
+ */
+SECTION Reservation_Table
+{
+  /* Simplifying assumption, ialu can execute all integer operations */
+  RL_IAlu       (use(any_normal_slot_t0_0 any_decoder_t1_1 arith_t2_2));
+  RL_IMul       (use(any_normal_slot_t0_0 any_decoder_t1_1 multdiv_t2_2));
+  RL_IDiv       (use(any_normal_slot_t0_0 any_decoder_t1_1 multdiv_t2_2));
+  RL_INOP       (use(any_normal_slot_t0_0 any_decoder_t1_1 nop_t2_2));
+  RL_ILogic     (use(any_normal_slot_t0_0 any_decoder_t1_1 logic_t2_2));
+  RL_IShiftBit  (use(any_normal_slot_t0_0 any_decoder_t1_1 shiftbit_t2_2));
+
+  /* Simplifying assumption, falu can execute all floating-point operations */
+  RL_FAlu       (use(any_normal_slot_t0_0 any_decoder_t1_1 farith_t2_2));
+  RL_FMul       (use(any_normal_slot_t0_0 any_decoder_t1_1 fmultdiv_t2_2));
+  RL_FDiv       (use(any_normal_slot_t0_0 any_decoder_t1_1 fmultdiv_t2_2));
+  RL_FRecSqrt   (use(any_normal_slot_t0_0 any_decoder_t1_1 frecsqrt_t2_2));
+  RL_FConv      (use(any_normal_slot_t0_0 any_decoder_t1_1 fconv_t2_2));
+
+  /* Simplifying assumption, mem unit can execute all memory operations */
+  RL_Load       (use(any_normal_slot_t0_0 any_decoder_t1_1 mem_t2_2));
+  RL_Store      (use(any_normal_slot_t0_0 any_decoder_t1_1 mem_t2_2));
+
+  /* Branches use branch slots (set above based on branch placement rules) 
+   * but otherwise act like normal operations.
+   */
+  RL_Branch     (use(any_branch_slot_t0_0 any_decoder_t1_1 branch_t2_2));
+  RL_JSR        (use(any_branch_slot_t0_0 any_decoder_t1_1 branch_t2_2));
+}
+
+/* Declare all the times that operands (s0, d1, etc) can be read/written to.
+ * These are used to determine register flow dependence latencies.
+ * 
+ * "Sync" operands (ss0, sd0, etc.) are used to determine memory, control, 
+ * and synchronization flow dependence latencies.
+ */
+SECTION Operand_Latency
+{
+  /* Declare all the times source operands can be read.
+   * Time 0 (for latencies) is assumed to be just before the first
+   * execution stage (when most source operands are read).
+   */
+  $for (I in 0 1) 
+  {
+      s${I}       (time(${I}));
+      p${I}       (time(${I}));
+  }
+
+  /* Declare all the times destination operands can be written to.
+   * Given the above assumption, this should be set to the operation latency.
+   * (Since the flow-dependence distance with be (dest_lat - src_lat).
+   */
+  $def LATENCIES {1 2 3 4 10 15}
+  $for (I in ${LATENCIES}) 
+  {
+      d${I}       (time(${I}));
+  }
+
+  /* Declare all the times sync source operands can be read. */
+  $for (I in 0) 
+  {
+      ss${I}      (time(${I}));
+  }
+
+  /* Declare all the times sync dest operands can be written to. */
+  $for (I in 0) 
+  {
+      sd${I}      (time(${I}));
+  }
+}
+
+/* Declare all the operation latency combinations allowed.
+ * The flow-dependence distance between two operands are determined
+ * with (dest_lat - src_lat).  So if dest_lat = 2, and src_lat = 0,
+ * a flow dependence with a two-cycle latency will be added.
+ */
+SECTION Operation_Latency
+{
+  /* Simplifying assumption, assume all sources are read at time 0, and
+   * destinations are written at their latency.  Assume all flow dependences
+   * between dependent memory and branch operations are 0 cycles.
+   */  
+  $for (I in ${LATENCIES}) 
+  {
+      Lat${I}     (dest(d${I} d${I} d${I} d${I})
+                   src(s0 s0 s0 s0 s0 s0)
+                   pred(p0)
+                   mem_dest(sd0)
+                   ctrl_dest(sd0)
+                   sync_dest(sd0)
+                   mem_src(ss0)
+                   ctrl_src(ss0)
+                   sync_src(ss0));               
+  }
+
+  LatDP1	(dest(d1 d1 d1 d1)
+                 src(s0 s0 s0 s0 s0 s0)
+                 pred(p${PBDELAY})
+                 mem_dest(sd0)
+                 ctrl_dest(sd0)
+                 sync_dest(sd0)
+                 mem_src(ss0)
+                 ctrl_src(ss0)
+                 sync_src(ss0));	
+
+}
+
+/* This section's entries group together an operation format, 
+ * reservation table,and an operation latency entry. 
+ * The requirements for all three entries need to be met in order for 
+ * the operation to be scheduled.
+ *
+ * Since we can model all the resource usage options with a single 
+ * AND/OR-tree-based reservation table and we have only one operation 
+ * format, we need only one scheduling alternative per operation type 
+ * to model resource constraints.
+ *
+ * However, if general speculation is enabled, create silent versions
+ * of operations that can except.
+ */
+SECTION Scheduling_Alternative
+{
+  ALT_IAlu      (format(A_AAAA_AAAAAA) resv (RL_IAlu) latency(Lat1));
+  ALT_IMul      (format(A_AAAA_AAAAAA) resv (RL_IMul) latency(Lat2));
+  ALT_IDiv      (format(A_AAAA_AAAAAA) resv (RL_IDiv) latency(Lat10));
+  ALT_INOP      (format(A_AAAA_AAAAAA) resv (RL_INOP) latency(Lat1));
+  ALT_ILogic    (format(A_AAAA_AAAAAA) resv (RL_ILogic) latency(Lat1));
+  ALT_IShiftBit (format(A_AAAA_AAAAAA) resv (RL_IShiftBit) latency(Lat1));
+
+  ALT_FAlu      (format(A_AAAA_AAAAAA) resv (RL_FAlu) latency(Lat3));
+  ALT_FMul      (format(A_AAAA_AAAAAA) resv (RL_FMul) latency(Lat4));
+  ALT_FDiv      (format(A_AAAA_AAAAAA) resv (RL_FDiv) latency(Lat15));
+  ALT_FRecSqrt  (format(A_AAAA_AAAAAA) resv (RL_FRecSqrt) latency(Lat2));
+  ALT_FConv     (format(A_AAAA_AAAAAA) resv (RL_FConv) latency(Lat4));
+
+  ALT_Load      (format(A_AAAA_AAAAAA) resv (RL_Load) latency(Lat4));
+  ALT_Store     (format(A_AAAA_AAAAAA) resv (RL_Store) latency(Lat1));
+
+  ALT_Branch    (format(A_AAAA_AAAAAA) resv (RL_Branch) latency(LatDP1));
+  ALT_JSR       (format(A_AAAA_AAAAAA) resv (RL_JSR) latency(Lat1));
+
+  /* Create silent versions of operations if non-trapping operations
+   * are specified as being supported.
+   */
+  ALT_IDiv_S     (format(A_AAAA_AAAAAA) resv (RL_IDiv) latency(Lat10) flags(SILENT));
+  ALT_FAlu_S     (format(A_AAAA_AAAAAA) resv (RL_FAlu) latency(Lat3) flags(SILENT));
+  ALT_FMul_S     (format(A_AAAA_AAAAAA) resv (RL_FMul) latency(Lat4) flags(SILENT));
+  ALT_FDiv_S     (format(A_AAAA_AAAAAA) resv (RL_FDiv) latency(Lat15) flags(SILENT));
+  ALT_FRecSqrt_S (format(A_AAAA_AAAAAA) resv (RL_FRecSqrt) latency(Lat2) flags(SILENT));
+  ALT_FConv_S    (format(A_AAAA_AAAAAA) resv (RL_FConv) latency(Lat4) flags(SILENT) );
+  ALT_Load_S     (format(A_AAAA_AAAAAA) resv (RL_Load) latency(Lat4) flags(SILENT));
+}
+
+/* This section entries groups together all the scheduling alternatives
+ * for each operation type.  In this simplified machine description, it
+ * is used only to add silent (non-trapping) versions of operations.
+ */
+SECTION Operation
+{
+  OP_IAlu       (alt(ALT_IAlu));    
+  OP_IMul       (alt(ALT_IMul));     
+  OP_IDiv       (alt(ALT_IDiv));     
+  OP_INOP       (alt(ALT_INOP));     
+  OP_ILogic	(alt(ALT_ILogic));
+  OP_IShiftBit	(alt(ALT_IShiftBit));
+
+  OP_FAlu       (alt(ALT_FAlu));     
+  OP_FMul       (alt(ALT_FMul));    
+  OP_FDiv       (alt(ALT_FDiv));     
+  OP_FRecSqrt	(alt(ALT_FRecSqrt));    
+  OP_FConv	(alt(ALT_FConv));     
+
+  OP_Load       (alt(ALT_Load));    
+  OP_Store      (alt(ALT_Store));   
+  OP_Branch     (alt(ALT_Branch));   
+  OP_JSR        (alt(ALT_JSR));     
+
+  OP_IDiv     (alt||(ALT_IDiv_S));     
+  OP_FMul     (alt||(ALT_FMul_S));    
+  OP_FAlu     (alt||(ALT_FAlu_S));     
+  OP_FDiv     (alt||(ALT_FDiv_S));     
+  OP_FRecSqrt (alt||(ALT_FRecSqrt_S));     
+  OP_FConv    (alt||(ALT_FConv_S));     
+  OP_Load     (alt||(ALT_Load_S));    
+}
+
+
+/* This section maps Lcode operations to scheduling alternatives (thru
+ * Operation entries).  It also describes to the scheduler and register
+ * allocator some properties of the operation (which they use instead
+ * of Lcode library calls).  It is very important to get these flags correct,
+ * otherwise the operation will be treated incorrectly and illegal
+ * schedules might result (i.e., must mark loads, stores, branches, etc.
+ * properly).
+ */
+SECTION IMPACT_Operation
+{
+  /* Compiler directives, the IGNORE flag tells the scheduler to ignore
+   * them (not schedule them, draw dependences to them, etc.) and put them 
+   * at the top of the cb after scheduling.  Just use OP_INOP since 
+   * something is needed.)
+   */
+  $for (OPC in Lop_DEFINE Lop_ALLOC Lop_PROLOGUE Lop_SIM_DIR Lop_BOUNDARY)
+  {
+      ${OPC}      (op(OP_INOP) flags (IGNORE));
+  }
+
+  /* EPILOGUE is a special compiler directive that must go just before
+   * the RTS (i.e, cannot move to top), so mark as SYNC operation
+   * (nothing will be able to move past it).
+   */
+  Lop_EPILOGUE  (op(OP_INOP) flags(SYNC));
+
+  /* INTRINSIC is a special opcode representing add-on instructions
+   * that can be emulated with C function calls.
+   */
+  Lop_INTRINSIC  (op(OP_INOP));
+
+  /* Don't expect any no-ops, however better define */
+  Lop_NO_OP     (op(OP_INOP));
+
+  /* General check */
+  Lop_CHECK     (op(OP_INOP) flags (CHK));
+
+  /* Jump subroutine opcodes, must be marked with JSR flag! */
+  $for (OPC in Lop_JSR Lop_JSR_FS)
+  {
+      ${OPC}      (op(OP_JSR) flags (JSR));
+  }
+
+  /* Return to subroutines opcodes, must be marked with RTS flag! */
+  $for (OPC in Lop_RTS Lop_RTS_FS)
+  {
+      ${OPC}      (op(OP_JSR) flags (RTS));
+  }
+
+  /* Unconditinal jump opcodes, must be marked with JMP flag! */
+  $for (OPC in Lop_JUMP Lop_JUMP_FS Lop_JUMP_RG Lop_JUMP_RG_FS)
+  {
+      ${OPC}      (op(OP_Branch) flags (JMP));
+  }
+
+  /* Conditional jump opcodes, must be marked with CBR flag!
+   * Assume branch unit can compare any type of operand.
+   */
+  $for (OPC in Lop_BEQ Lop_BEQ_FS Lop_BNE Lop_BNE_FS
+               Lop_BGT Lop_BGT_FS Lop_BGE Lop_BGE_FS
+               Lop_BLT Lop_BLT_FS Lop_BLE Lop_BLE_FS
+               Lop_BGT_U Lop_BGT_U_FS Lop_BGE_U Lop_BGE_U_FS
+               Lop_BLT_U Lop_BLT_U_FS Lop_BLE_U Lop_BLE_U_FS
+               Lop_BEQ_F Lop_BEQ_F_FS Lop_BNE_F Lop_BNE_F_FS
+               Lop_BGT_F Lop_BGT_F_FS Lop_BGE_F Lop_BGE_F_FS
+               Lop_BLT_F Lop_BLT_F_FS Lop_BLE_F Lop_BLE_F_FS
+               Lop_BEQ_F2 Lop_BEQ_F2_FS Lop_BNE_F2 Lop_BNE_F2_FS
+               Lop_BGT_F2 Lop_BGT_F2_FS Lop_BGE_F2 Lop_BGE_F2_FS
+               Lop_BLT_F2 Lop_BLT_F2_FS Lop_BLE_F2 Lop_BLE_F2_FS
+	       Lop_BR Lop_BR_F)
+  {
+      ${OPC}      (op(OP_Branch) flags (CBR));
+  }
+
+  /* Integer Ialu operations, no flags needed */
+  $for (OPC in Lop_MOV Lop_ABS Lop_ADD
+               Lop_L_MAC Lop_L_MSU Lop_ADD_SAT Lop_ADD_SAT_U
+               Lop_SUB_SAT Lop_SUB_SAT_U 
+               Lop_SAT Lop_SAT_U
+               Lop_ADD_U Lop_SUB Lop_SUB_U Lop_EQ
+               Lop_NE Lop_GT Lop_GT_U Lop_GE Lop_GE_U 
+               Lop_LT Lop_LT_U Lop_LE Lop_LE_U 
+	       Lop_EXTRACT_C Lop_EXTRACT_C2 Lop_EXTRACT Lop_EXTRACT_U Lop_DEPOSIT
+	       Lop_CMP Lop_RCMP Lop_PRED_COPY)
+  {
+      ${OPC}      (op(OP_IAlu));
+  }
+
+  /* Integer multiple operations, no flags needed.
+   * Simplified, treat multiply_add ops, etc same as multiply.
+   */
+  $for (OPC in Lop_MUL Lop_MUL_U Lop_MUL_ADD Lop_MUL_ADD_U Lop_MUL_SAT Lop_MUL_SAT_U
+               Lop_MUL_SUB Lop_MUL_SUB_U Lop_MUL_SUB_REV Lop_MUL_SUB_REV_U)
+  {
+      ${OPC}      (op(OP_IMul));
+  }
+
+  /* Integer divide operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_DIV Lop_DIV_U Lop_REM Lop_REM_U)
+  {
+      ${OPC}      (op(OP_IDiv) flags (EXCEPT));
+  }
+
+  /* Integer logic operations, no flags needed */
+  $for (OPC in Lop_OR Lop_AND 
+               Lop_XOR Lop_NOR Lop_NAND Lop_NXOR      
+               Lop_OR_NOT Lop_AND_NOT Lop_OR_COMPL Lop_AND_COMPL)
+  {
+      ${OPC}      (op(OP_ILogic));
+  }
+
+  /* Integer shift and bit manipulation operations, no flags needed */
+  $for (OPC in Lop_LSL Lop_LSR Lop_ASR Lop_LSLADD 
+	       Lop_SXT_C Lop_SXT_C2 Lop_SXT_I Lop_ZXT_C Lop_ZXT_C2 Lop_ZXT_I)
+  {
+      ${OPC}      (op(OP_IShiftBit));
+  }
+
+  /* Floating-point moves, cannot except */
+  Lop_MOV_F     (op(OP_FAlu));
+  Lop_MOV_F2    (op(OP_FAlu));
+
+  /* Floating-point alu operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_ABS_F Lop_ABS_F2 Lop_ADD_F Lop_ADD_F2
+               Lop_SUB_F Lop_SUB_F2 Lop_EQ_F Lop_EQ_F2
+               Lop_NE_F Lop_NE_F2 Lop_GT_F Lop_GT_F2
+               Lop_GE_F Lop_GE_F2 Lop_LT_F Lop_LT_F2
+               Lop_LE_F Lop_LE_F2 Lop_CMP_F Lop_RCMP_F)
+  {
+      ${OPC}      (op(OP_FAlu) flags (EXCEPT));
+  }
+
+  /* Floating-point Conv operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_I_F Lop_F_I
+               Lop_I_F2 Lop_F2_I Lop_F_F2 Lop_F2_F)
+  {
+      ${OPC}      (op(OP_FConv) flags (EXCEPT));
+  }
+
+  /* Floating-point multiple operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   * Simplified, treat multiply_add ops, etc same as multiply.
+   */
+  $for (OPC in Lop_MUL_F Lop_MUL_F2 Lop_MUL_ADD_F Lop_MUL_ADD_F2
+               Lop_MUL_SUB_F Lop_MUL_SUB_REV_F 
+               Lop_MUL_SUB_F2 Lop_MUL_SUB_REV_F2)
+  {
+      ${OPC}      (op(OP_FMul) flags (EXCEPT));
+  }
+
+  /* Floating-point divide operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   * Simplified, treat sqrt ops, etc same as divide.
+   */
+  $for (OPC in Lop_DIV_F Lop_DIV_F2)
+  {
+      ${OPC}      (op(OP_FDiv) flags (EXCEPT));
+  }
+
+  $for (OPC in Lop_SQRT_F Lop_SQRT_F2)
+  {
+      ${OPC}      (op(OP_FRecSqrt) flags (EXCEPT));
+  }
+
+  /* Loop over the possible data types for memory operations */
+  $for (TYPE in C C2 I Q F F2)
+  {
+    /* Load memory opcodes, must be marked with EXCEPT LOAD flag! 
+     * Will not speculate above branch unless one of the scheduling
+     * alternatives is a SILENT version.
+     * Pre and post increment loads (LD_PRE, LD_POST) are not currently 
+     * supported (as of IMPACT release 2.32).
+     */
+     Lop_LD_${TYPE} (op(OP_Load) flags (EXCEPT LOAD));
+
+
+    /* Store memory opcodes, must be marked with EXCEPT STORE flag! 
+     * Pre and post increment stores (ST_PRE, ST_POST) are not currently 
+     * supported (as of IMPACT release 2.32).
+     */
+     Lop_ST_${TYPE} (op(OP_Store) flags (EXCEPT STORE));
+  }
+
+  /* Unsigned character/short loads (there are no unsigned stores) */
+  Lop_LD_UC       (op(OP_Load) flags (EXCEPT LOAD));
+  Lop_LD_UC2      (op(OP_Load) flags (EXCEPT LOAD));
+  Lop_LD_UI       (op(OP_Load) flags (EXCEPT LOAD));
+
+  /* Predicate load/store operations */
+  Lop_PRED_LD     (op(OP_Load) flags(EXCEPT LOAD));
+  Lop_PRED_ST     (op(OP_Store) flags(EXCEPT STORE));
+
+  /* Load/store block of 32 predicate registers (used by register allocator) */
+  Lop_PRED_LD_BLK (op(OP_Load) flags(EXCEPT LOAD));
+  Lop_PRED_ST_BLK (op(OP_Store) flags(EXCEPT STORE));
+
+  /* PRED_CLEAR and PRED_SET clears/sets a single predicate, primarily for 
+   * the convenence of the compiler writer. They need to be folded into
+   * later predicate definitions (via optimizations) and the rest converted 
+   * into operations that set/clear multiple predicates (perhaps up to 32) 
+   * in a single operation.  Since these pred clear/set optimizations are
+   * not currently supported (as of IMPACT release 2.32), make an aggressive 
+   * assumption that they are free and ignore their cost by treating them 
+   * as compiler directives.  (The alternative, to treat them as regular 
+   * operations is way too conservative, since many of them can be folded 
+   * in with later predicate definitions (thus eliminated) and the rest
+   * can be converted into at least predicate definitions (which allow
+   * setting two predicates per operation).
+   */
+  Lop_PRED_CLEAR(op(OP_IAlu) flags(IGNORE));
+  Lop_PRED_SET  (op(OP_IAlu) flags(IGNORE));
+
+  /* Predicate definition opcodes using integer comparisons.
+   * No flags needed. 
+   */
+  $for (OPC in Lop_PRED_EQ Lop_PRED_NE Lop_PRED_GT Lop_PRED_GT_U 
+               Lop_PRED_GE Lop_PRED_GE_U Lop_PRED_LT Lop_PRED_LT_U
+               Lop_PRED_LE Lop_PRED_LE_U)
+  {
+      ${OPC}      (op(OP_IAlu));
+  }
+
+  /* Predicate definition opcodes using floating-point comparisons.
+   * EXCEPT flag must be specified. Will not speculate above branch
+   * unless one of the scheduling alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_PRED_EQ_F2 Lop_PRED_NE_F2 Lop_PRED_GT_F2 Lop_PRED_GE_F2
+               Lop_PRED_LT_F2 Lop_PRED_LE_F2 Lop_PRED_EQ_F Lop_PRED_NE_F
+               Lop_PRED_GT_F Lop_PRED_GE_F Lop_PRED_LT_F Lop_PRED_LE_F)
+  {
+      ${OPC}      (op(OP_FAlu) flags (EXCEPT));
+  }
+}
+
+
+
diff -urN openimpact-1.0rc4/mdes/Limpact/IMPACT_BASE_TEMPLATE.hmdes2 openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_BASE_TEMPLATE.hmdes2
--- openimpact-1.0rc4/mdes/Limpact/IMPACT_BASE_TEMPLATE.hmdes2	1969-12-31 18:00:00.000000000 -0600
+++ openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_BASE_TEMPLATE.hmdes2	2004-09-17 14:41:02.000000000 -0500
@@ -0,0 +1,864 @@
+/*****************************************************************************\
+ *
+ *		      Illinois Open Source License
+ *                     University of Illinois/NCSA
+ *                         Open Source License
+ *
+ * Copyright (c) 2004, The University of Illinois at Urbana-Champaign.
+ * All rights reserved.
+ *
+ * Developed by:             
+ *
+ *		IMPACT Research Group
+ *
+ *		University of Illinois at Urbana-Champaign
+ *
+ *              http://www.crhc.uiuc.edu/IMPACT
+ *              http://www.gelato.org
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal with the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimers.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimers in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the names of the IMPACT Research Group, the University of
+ * Illinois, nor the names of its contributors may be used to endorse
+ * or promote products derived from this Software without specific
+ * prior written permission.  THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
+ * LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+ * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS WITH THE SOFTWARE.
+ *
+\*****************************************************************************/
+/*****************************************************************************\
+ *
+ *  File:  IMPACT_BASE_TEMPLATE.hmdes2
+ *
+ *  Description:  Simple machine description template for wide-variety of 
+ *                experimental processors that execute IMPACT's Lcode.
+ *                This simplified template does not model register ports and
+ *                uses a fairly simple function unit model.  It is designed
+ *                to be relatively easy to understand and modify.  
+ * 
+ *  Note: For hmdes2 documentation (slightly out-of-date), see:
+ * 
+ *          HMDES Version 2 Specification 
+ *          John C. Gyllenhaal, Wen-mei W. Hwu and B. Ramakrishna Rau
+ *          IMPACT Technical report, IMPACT-96-03, 
+ *          University of Illinois, Urbana IL. 1996.
+ *          http://www.crhc.uiuc.edu/IMPACT/ftp/report/impact-96-03.hmdes2.pdf
+ *
+ *  Note: Although IMPACT's and HPL's (Elcor) machine descriptions share a 
+ *        common host language "MD" (aka as "dabble" at HPL), they are not 
+ *        currently compatible with each other.  This machine description 
+ *        cannot be used with Trimaran's Elcor-based scheduler and Elcor's
+ *        machine descriptions cannot be used with IMPACT-based schedulers.
+ *        
+ *  Creation Date :  June 1999
+ *
+ *  Author:  John C. Gyllenhaal, Wen-mei Hwu
+ *
+ *  Revisions:
+ *
+\*****************************************************************************/
+
+/* Read in the IMPACT's expected structure for this .hmdes2 file */
+$include "${IMPACT_REL_PATH}/mdes/structure/structure_IMPACT.hmdes2"
+
+/* 
+ * Processor resource configuration parameters. 
+ */
+
+$def WIDTH              8
+$def NUM_IALUS          ${WIDTH}
+$def NUM_FALUS          ${WIDTH}
+$def NUM_MEM_UNITS      ${WIDTH}
+$def NUM_BRANCHES       ${WIDTH}
+
+/*
+ * Cycle in which UBR / CBR load source predicate.  Setting to 1 instead
+ * of 0 yields a 0-cycle-delay between pred defines and branches.
+ */
+$def PBDELAY            0
+
+/* 
+ * Processor issue-rule configuration parameters. 
+ */
+$def BRANCHES_AT_END    1  // If 1, places branches at end of each instr packet
+$def NON_TRAPPING_OPS   1  // If 1, allow general speculation
+
+
+/* 
+ * Scheduling 'slots' are used by the scheduler to determine ordering of 
+ * operations within an operation packet (operations scheduled to execute 
+ * in the same cycle).  The 'decoder' resources are used by this machine
+ * description to set the maximum number of operations that can be issued 
+ * per cycle (WIDTH).  The 'branch' resources are used by this
+ * machine description to set the maximum number of branches that can
+ * be issued per cycle (NUM_BRANCHES).
+ *
+ * If there are no constraints on operation ordering within the packet
+ * (i.e., branches can be scheduled anywhere), we will create the same
+ * number of slots as decoders.  
+ *
+ *   Example SS_3G_2BX (3-issue, 2 branches anywhere):
+ *          slot0: any operation (branch or non-branch)
+ *          slot1: any operation 
+ *          slot2: any operation 
+ *       decoder1: any operation
+ *       decoder2: any operation
+ *       decoder3: any operation
+ *        branch1: any branch
+ *        branch2: any branch
+ *
+ *
+ * If branches must be placed at the end, but there is only one branch,
+ * we still create the same number of slots as decoders and just
+ * require branches to use the last slot.
+ *
+ *   Example SS_3G_1BL (3-issue, 1 branch last):
+ *          slot0: non-branch operation 
+ *          slot1: non-branch operation 
+ *          slot2: any operation 
+ *       decoder1: any operation
+ *       decoder2: any operation
+ *       decoder3: any operation
+ *        branch1: any branch
+ *
+ * If branches must be placed at the end, but there are more than one branch,
+ * we need to create more slots than decoders, in order to force branches
+ * to the end.  Although there are more slots in this case, the decoders
+ * still limit the operations per cycle (to WIDTH).
+ *
+ *   Example SS_3G_2BL (3-issue, 2 branches last):
+ *          slot0: non-branch operation   <- add1
+ *          slot1: non-branch operation   <- (not used)
+ *          slot2: any operation          <- branch1
+ *          slot3: branch operation       <- branch2
+ *       decoder1: any operation          <- add1
+ *       decoder2: any operation          <- branch1
+ *       decoder3: any operation          <- branch2
+ *        branch1: any branch             <- branch1
+ *        branch2: any branch             <- branch2
+ *
+ *  Example of why using the same number of slots does not work for SS_3G_2BL:
+ *          slot0: non-branch operation   <- add1
+ *          slot1: any operation          <- branch1
+ *          slot2: any operation          <- add2    (*not allowed*)
+ *       decoder1: any operation          <- add1
+ *       decoder2: any operation          <- branch1
+ *       decoder3: any operation          <- add2
+ *        branch1: any branch             <- branch1
+ *        branch2: any branch             <- (not used)
+ * 
+ * In the SS_3G_2BL example, it is *still* a three issue processor even
+ * though it has four issue slots!
+ *
+ * For historical reasons, the scheduler tools expect the slots to be
+ * numbered slot0,...slotN.
+ */
+$if (${BRANCHES_AT_END} == 1)
+{
+    /* Create the minimum number of slots that allow us to force
+     * branches to the end of the operation packet.
+     */
+    $def LAST_SLOT $={ (${WIDTH}-1) + (${NUM_BRANCHES}-1) }
+}
+$else
+{
+    /* Otherwise, just create one slot per decoder */
+    $def LAST_SLOT $={${WIDTH}-1}
+}
+
+
+/* Section for passing parameters to IMPACT's scheduler and 
+ * lmdes2_customizer 
+ */
+SECTION Parameter
+{
+  /* Used by lmdes2_customizer to assign integer numbers to many of the
+   * strings in this machine description, such as Lop_ADD, Label, REG
+   * EXCEPT, LOAD, etc.
+   */
+  customization_headers
+                (value("${IMPACT_ROOT}/include/Lcode/l_opc.h"
+                       "${IMPACT_ROOT}/include/Lcode/l_flags.h"
+                       "${IMPACT_ROOT}/include/Lcode/limpact_phase1.h"
+                       "${IMPACT_ROOT}/include/machine/m_spec.h"
+                       "${IMPACT_ROOT}/include/machine/m_impact.h"));
+
+  /* Phased out in version 2.31, but should always be set to "superscalar" 
+   * for backward compatibilty and so lmdes2_customizer does not complain.
+   * It is OK to set this to superscalar when targeting an EPIC processor!
+   */
+  processor_model (value("superscalar"));
+
+}
+
+/* Convert the scheduler operand types (NULL, p, i, f, f2, Label, and Lit)
+ * into the short name (A) that will be used to describe 
+ * the operation format mapping entries in Operation_Format.
+ */
+SECTION Field_Type
+{
+  /* Names the scheduler (thru Mspec) will use to describe the operands */
+  NULL ();                              // No operand allowed
+  p ();                                 // Predicate register operand 
+  i ();                                 // Integer register operand 
+  f ();                                 // Float register operand 
+  f2 ();                                // Double register operand 
+  Label ();                             // Generic label literal
+  Lit ();			        // Generic non-label literal
+  REG (compatible_with (i f f2));      // Generic register operand
+
+  /* Remap and group the names above into one letter names for ease of use 
+   * below in Operation Format.  Since not modeling register port usage
+   * in this template, just map everything to 'A'.
+   */
+  A (compatible_with (NULL p i f f2 Label Lit REG)); // Anything allowed
+}
+
+/* Define all the operation formats supported in the target machine.
+ *
+ * All entrys are in the form:
+ *   P0_D0D1_S0S1S2  
+ *
+ * where:
+ *   P0       is the pred[0] operand specifier 
+ *   D0       is the dest[0] operand specifier 
+ *   D1       is the dest[1] operand specifier 
+ *   S0       is the src[0] operand specifier 
+ *   S1       is the src[1] operand specifier 
+ *   S2       is the src[2] operand specifier 
+ *   
+ * Since in this template, we are not modeling register port usage, only
+ * one operation format is needed (significantly simplifying the rest of
+ * the machine description).
+ */
+SECTION Operation_Format
+{
+  A_AAAA_AAAAAA                       (pred (A) dest (A A A A) src (A A A A A A));
+}
+
+
+/*
+ *  Declare the processor resources that we wish to model.
+ *
+ *  Note: The resource names (such as decoder1) are *not* keywords.
+ *        Renaming all the resources to r1, r2, r3... r30 (and 
+ *        their references) will yield the exact same schedule.
+ *
+ *  Note: You can use as many or few resources as desired in order
+ *        to model the processor's execution constraints.  Typically,
+ *        we don't model anything that doesn't add execution constraints
+ *        (e.g., pipeline stages in fully-pipelined function units, etc.).
+ *         
+ *
+ *  Note: The 'slot' field is used to associate slot ids with particular
+ *        resource names.  For simplicity, we assign slot id 0, to slot0,
+ *        etc.  Not defining the 'slot' field indicates that this is 
+ *        a non-slot (i.e., normal) resource.
+ *        For example, to associate scheduler slot 3, with resource 
+ *        'my_slot_3':
+ *           my_slot_3 (slot(3));
+ */
+SECTION Resource
+{
+  /* Slots are used to control how operations are scheduled within the
+   * same cycle (instruction packet).  For historical reasons, slots
+   * are numbered starting from 0 (the first slot in the packet).
+   */
+  $for (I in $0..${LAST_SLOT})
+  {
+      slot${I} (slot(${I}));
+  }
+
+  /* Decoders are used to limit the number of operations that can
+   * issue in one cycle.
+   */
+  $for (I in $1..${WIDTH})
+  {
+      decoder${I} ();
+  }
+
+  /* Create the various functional units for this machine
+   * Note: All these units are assumed to be fully pipelined, so
+   *       we only need to model the first stage.
+   */
+  $for (I in $1..${NUM_IALUS})
+  {
+      ialu${I} ();
+  }
+
+  $for (I in $1..${NUM_FALUS})
+  {
+      falu${I} ();
+  }
+
+  $for (I in $1..${NUM_BRANCHES})
+  {
+      branch${I} ();
+  }
+
+  $for (I in $1..${NUM_MEM_UNITS})
+  {
+      mem${I} ();
+  }
+}
+
+/*
+ * Specify the possible times in the pipeline the resources can be 
+ * used.  Here is the time mapping used in this machine description
+ * for resource usages:
+ * 
+ *   0 -> Fetch stage
+ *   1 -> Decode stage
+ *   2 -> First execution stage
+ *   3 -> Second execution stage and write-back stage for latency 1 ops
+ *   4 -> Third execution stage and write-back stage for latency 2 ops
+ *   etc.
+ */
+SECTION Resource_Usage
+{
+
+  /*
+   * Fetch stage
+   */    
+  $for (I in $0..${LAST_SLOT})
+  {
+      RU_slot${I}_t0_0 (use(slot${I}) time (0));
+  }
+
+
+  /*
+   * Decoder stage
+   */
+  $for (I in $1..${WIDTH})
+  {
+      RU_decoder${I}_t1_1 (use(decoder${I}) time (1));
+  }
+
+
+  /*
+   * First execution stage
+   */
+  $for (I in $1..${NUM_IALUS})
+  {
+      RU_ialu${I}_t2_2 (use(ialu${I}) time (2));
+  }
+
+  $for (I in $1..${NUM_FALUS})
+  {
+      RU_falu${I}_t2_2 (use(falu${I}) time (2));
+  }
+
+  $for (I in $1..${NUM_BRANCHES})
+  {
+      RU_branch${I}_t2_2 (use(branch${I}) time (2));
+  }
+
+  $for (I in $1..${NUM_MEM_UNITS})
+  {
+      RU_mem${I}_t2_2 (use(mem${I}) time (2));
+  }
+
+  /*
+   * Second execution stage and write-back stage for latency 1 ops
+   * etc.
+   */
+  /*
+   * We are assuming fully-pipelined functional units, so later
+   * stages do not need to be modeled.  We are not modeling register
+   * ports, so the write-backs don't need to be modeled.
+   */
+}
+
+/* Group together resource usages that should always be used together.
+ * None necessary for this simplified machine description.
+ */
+SECTION Resource_Unit
+{ 
+}
+
+/* Create options where any one of the options may be selected.
+ * For example, any one of the declared IALUs may be used.
+ *
+ * Note: Table options are used to create the OR part of AND/OR-trees.
+ */
+SECTION Table_Option
+{
+  /* Use any "normal" slot for non-branch operations. */
+  any_normal_slot_t0_0 
+  (
+      one_of($for (I in $0..(${WIDTH}-1)) {RU_slot${I}_t0_0 })
+  );
+
+  /* If placing branches at end, branches can only use the last normal
+   * slot and the extra slots after the normal slots (if 2 or more branches).
+   */
+  $if (${BRANCHES_AT_END} == 1)
+  {
+      any_branch_slot_t0_0
+      (
+          one_of($for (I in $(${WIDTH}-1)..${LAST_SLOT}){RU_slot${I}_t0_0 })
+      );
+  }
+  /* Otherwise, can place branch in any normal slot, just like non-branch ops*/
+  $else
+  {
+      any_branch_slot_t0_0 
+      (
+          one_of($for (I in $0..(${WIDTH}-1)) {RU_slot${I}_t0_0 })
+      );
+  }
+
+  /* 
+   * Allow any of the decoders to be used. 
+   * This resource use limits the processor's issue width, not slots.
+   */
+  any_decoder_t1_1 
+  (
+      one_of($for (I in $1..${WIDTH}){RU_decoder${I}_t1_1 })
+  );
+
+  /* 
+   * Allow any of the declared functional units to be used 
+   */
+  any_ialu_t2_2 
+  (
+      one_of($for (I in $1..${NUM_IALUS}) {RU_ialu${I}_t2_2 })
+  );
+
+  any_falu_t2_2 
+  (
+      one_of($for (I in $1..${NUM_FALUS}) {RU_falu${I}_t2_2 })
+  );
+
+  any_mem_t2_2 
+  (
+      one_of($for (I in $1..${NUM_MEM_UNITS}) {RU_mem${I}_t2_2 })
+  );
+
+  any_branch_t2_2 
+  (
+      one_of($for (I in $1..${NUM_BRANCHES}) {RU_branch${I}_t2_2 })
+  );
+}
+
+/* Create the AND-OR trees that describes the how the processor resources
+ * are used as the operation executes.  This is the AND part of the
+ * AND/OR-tree representation for reservation tables.
+ *
+ * Any mixture of Table_Option, Resource_Unit, and Resource Usage entries
+ * may be specified in the 'use' field.
+ */
+SECTION Reservation_Table
+{
+  /* Simplifying assumption, ialu can execute all integer operations */
+  RL_IAlu       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_ialu_t2_2));
+  RL_IMul       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_ialu_t2_2));
+  RL_IDiv       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_ialu_t2_2));
+  RL_INOP       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_ialu_t2_2));
+
+  /* Simplifying assumption, falu can execute all floating-point operations */
+  RL_FAlu       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_falu_t2_2));
+  RL_FMul       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_falu_t2_2));
+  RL_FDiv       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_falu_t2_2));
+
+  /* Simplifying assumption, mem unit can execute all memory operations */
+  RL_Load       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_mem_t2_2));
+  RL_Store      (use(any_normal_slot_t0_0 any_decoder_t1_1 any_mem_t2_2));
+
+  /* Branches use branch slots (set above based on branch placement rules) 
+   * but otherwise act like normal operations.
+   */
+  RL_Branch     (use(any_branch_slot_t0_0 any_decoder_t1_1 any_branch_t2_2));
+  RL_JSR        (use(any_branch_slot_t0_0 any_decoder_t1_1 any_branch_t2_2));
+}
+
+/* Declare all the times that operands (s0, d1, etc) can be read/written to.
+ * These are used to determine register flow dependence latencies.
+ * 
+ * "Sync" operands (ss0, sd0, etc.) are used to determine memory, control, 
+ * and synchronization flow dependence latencies.
+ */
+SECTION Operand_Latency
+{
+  /* Declare all the times source operands can be read.
+   * Time 0 (for latencies) is assumed to be just before the first
+   * execution stage (when most source operands are read).
+   */
+  $for (I in 0 1) 
+  {
+      s${I}       (time(${I}));
+      p${I}       (time(${I}));
+  }
+
+  /* Declare all the times destination operands can be written to.
+   * Given the above assumption, this should be set to the operation latency.
+   * (Since the flow-dependence distance with be (dest_lat - src_lat).
+   */
+  $def LATENCIES {1 2 3 15}
+  $for (I in ${LATENCIES}) 
+  {
+      d${I}       (time(${I}));
+  }
+
+  /* Declare all the times sync source operands can be read. */
+  $for (I in 0) 
+  {
+      ss${I}      (time(${I}));
+  }
+
+  /* Declare all the times sync dest operands can be written to. */
+  $for (I in 0) 
+  {
+      sd${I}      (time(${I}));
+  }
+}
+
+/* Declare all the operation latency combinations allowed.
+ * The flow-dependence distance between two operands are determined
+ * with (dest_lat - src_lat).  So if dest_lat = 2, and src_lat = 0,
+ * a flow dependence with a two-cycle latency will be added.
+ */
+SECTION Operation_Latency
+{
+  /* Simplifying assumption, assume all sources are read at time 0, and
+   * destinations are written at their latency.  Assume all flow dependences
+   * between dependent memory and branch operations are 0 cycles.
+   */  
+  $for (I in ${LATENCIES}) 
+  {
+      Lat${I}     (dest(d${I} d${I} d${I} d${I})
+                   src(s0 s0 s0 s0 s0 s0)
+                   pred(p0)
+                   mem_dest(sd0)
+                   ctrl_dest(sd0)
+                   sync_dest(sd0)
+                   mem_src(ss0)
+                   ctrl_src(ss0)
+                   sync_src(ss0));               
+  }
+
+  LatDP1	(dest(d1 d1 d1 d1)
+                 src(s0 s0 s0 s0 s0 s0)
+                 pred(p${PBDELAY})
+                 mem_dest(sd0)
+                 ctrl_dest(sd0)
+                 sync_dest(sd0)
+                 mem_src(ss0)
+                 ctrl_src(ss0)
+                 sync_src(ss0));	
+
+}
+
+/* This section's entries group together an operation format, 
+ * reservation table,and an operation latency entry. 
+ * The requirements for all three entries need to be met in order for 
+ * the operation to be scheduled.
+ *
+ * Since we can model all the resource usage options with a single 
+ * AND/OR-tree-based reservation table and we have only one operation 
+ * format, we need only one scheduling alternative per operation type 
+ * to model resource constraints.
+ *
+ * However, if general speculation is enabled, create silent versions
+ * of operations that can except.
+ */
+SECTION Scheduling_Alternative
+{
+  ALT_IAlu     (format(A_AAAA_AAAAAA) resv (RL_IAlu) latency(Lat1));
+  ALT_IMul     (format(A_AAAA_AAAAAA) resv (RL_IAlu) latency(Lat2));
+  ALT_IDiv     (format(A_AAAA_AAAAAA) resv (RL_IAlu) latency(Lat15));
+  ALT_INOP     (format(A_AAAA_AAAAAA) resv (RL_IAlu) latency(Lat1));
+  ALT_FAlu     (format(A_AAAA_AAAAAA) resv (RL_FAlu) latency(Lat2));
+  ALT_FMul     (format(A_AAAA_AAAAAA) resv (RL_FAlu) latency(Lat2));
+  ALT_FDiv     (format(A_AAAA_AAAAAA) resv (RL_FAlu) latency(Lat15));
+  ALT_Load     (format(A_AAAA_AAAAAA) resv (RL_Load) latency(Lat3));
+  ALT_Store    (format(A_AAAA_AAAAAA) resv (RL_Store) latency(Lat1));
+  ALT_Branch   (format(A_AAAA_AAAAAA) resv (RL_Branch) latency(LatDP1));
+  ALT_JSR      (format(A_AAAA_AAAAAA) resv (RL_JSR) latency(Lat1));
+
+  /* Create silent versions of operations if non-trapping operations
+   * are specified as being supported.
+   */
+  $if(${NON_TRAPPING_OPS} == 1) 
+  {
+    ALT_IDiv_S (format(A_AAAA_AAAAAA) resv (RL_IAlu) latency(Lat15) flags(SILENT));
+    ALT_FAlu_S (format(A_AAAA_AAAAAA) resv (RL_FAlu) latency(Lat2) flags(SILENT));
+    ALT_FMul_S (format(A_AAAA_AAAAAA) resv (RL_FAlu) latency(Lat2) flags(SILENT));
+    ALT_FDiv_S (format(A_AAAA_AAAAAA) resv (RL_FAlu) latency(Lat15) flags(SILENT));
+    ALT_Load_S (format(A_AAAA_AAAAAA) resv (RL_Load) latency(Lat3) flags(SILENT));
+  }
+}
+
+/* This section entries groups together all the scheduling alternatives
+ * for each operation type.  In this simplified machine description, it
+ * is used only to add silent (non-trapping) versions of operations.
+ */
+SECTION Operation
+{
+  OP_IAlu       (alt(ALT_IAlu));    
+  OP_IMul       (alt(ALT_IMul));     
+  OP_IDiv       (alt(ALT_IDiv));     
+  OP_INOP       (alt(ALT_INOP));     
+  OP_FAlu       (alt(ALT_FAlu));     
+  OP_FMul       (alt(ALT_FMul));    
+  OP_FDiv       (alt(ALT_FDiv));     
+  OP_Load       (alt(ALT_Load));    
+  OP_Store      (alt(ALT_Store));   
+  OP_Branch     (alt(ALT_Branch));   
+  OP_JSR        (alt(ALT_JSR));     
+
+  /* Add silent versions to above (excepting) alternative lists,
+   *  if non-trapping operations are specified as being supported.
+   */
+  $if(${NON_TRAPPING_OPS} == 1) 
+  {
+    OP_IDiv     (alt||(ALT_IDiv_S));     
+    OP_FMul     (alt||(ALT_FMul_S));    
+    OP_FAlu     (alt||(ALT_FAlu_S));     
+    OP_FDiv     (alt||(ALT_FDiv_S));     
+    OP_Load     (alt||(ALT_Load_S));    
+  }
+}
+
+
+/* This section maps Lcode operations to scheduling alternatives (thru
+ * Operation entries).  It also describes to the scheduler and register
+ * allocator some properties of the operation (which they use instead
+ * of Lcode library calls).  It is very important to get these flags correct,
+ * otherwise the operation will be treated incorrectly and illegal
+ * schedules might result (i.e., must mark loads, stores, branches, etc.
+ * properly).
+ */
+SECTION IMPACT_Operation
+{
+  /* Compiler directives, the IGNORE flag tells the scheduler to ignore
+   * them (not schedule them, draw dependences to them, etc.) and put them 
+   * at the top of the cb after scheduling.  Just use OP_INOP since 
+   * something is needed.)
+   */
+  $for (OPC in Lop_DEFINE Lop_ALLOC Lop_PROLOGUE Lop_SIM_DIR Lop_BOUNDARY)
+  {
+      ${OPC}      (op(OP_INOP) flags (IGNORE));
+  }
+
+  /* EPILOGUE is a special compiler directive that must go just before
+   * the RTS (i.e, cannot move to top), so mark as SYNC operation
+   * (nothing will be able to move past it).
+   */
+  Lop_EPILOGUE  (op(OP_INOP) flags(SYNC));
+
+  /* INTRINSIC is a special opcode representing add-on instructions
+   * that can be emulated with C function calls.
+   */
+  Lop_INTRINSIC  (op(OP_INOP));
+
+  /* Don't expect any no-ops, however better define */
+  Lop_NO_OP     (op(OP_INOP));
+
+  /* General check */
+  Lop_CHECK     (op(OP_INOP) flags (CHK));
+
+  /* Jump subroutine opcodes, must be marked with JSR flag! */
+  $for (OPC in Lop_JSR Lop_JSR_FS)
+  {
+      ${OPC}      (op(OP_JSR) flags (JSR));
+  }
+
+  /* Return to subroutines opcodes, must be marked with RTS flag! */
+  $for (OPC in Lop_RTS Lop_RTS_FS)
+  {
+      ${OPC}      (op(OP_JSR) flags (RTS));
+  }
+
+  /* Unconditinal jump opcodes, must be marked with JMP flag! */
+  $for (OPC in Lop_JUMP Lop_JUMP_FS Lop_JUMP_RG Lop_JUMP_RG_FS)
+  {
+      ${OPC}      (op(OP_Branch) flags (JMP));
+  }
+
+  /* Conditional jump opcodes, must be marked with CBR flag!
+   * Assume branch unit can compare any type of operand.
+   */
+  $for (OPC in Lop_BR Lop_BR_F Lop_BEQ Lop_BEQ_FS Lop_BNE Lop_BNE_FS
+               Lop_BGT Lop_BGT_FS Lop_BGE Lop_BGE_FS
+               Lop_BLT Lop_BLT_FS Lop_BLE Lop_BLE_FS
+               Lop_BGT_U Lop_BGT_U_FS Lop_BGE_U Lop_BGE_U_FS
+               Lop_BLT_U Lop_BLT_U_FS Lop_BLE_U Lop_BLE_U_FS
+               Lop_BEQ_F Lop_BEQ_F_FS Lop_BNE_F Lop_BNE_F_FS
+               Lop_BGT_F Lop_BGT_F_FS Lop_BGE_F Lop_BGE_F_FS
+               Lop_BLT_F Lop_BLT_F_FS Lop_BLE_F Lop_BLE_F_FS
+               Lop_BEQ_F2 Lop_BEQ_F2_FS Lop_BNE_F2 Lop_BNE_F2_FS
+               Lop_BGT_F2 Lop_BGT_F2_FS Lop_BGE_F2 Lop_BGE_F2_FS
+               Lop_BLT_F2 Lop_BLT_F2_FS Lop_BLE_F2 Lop_BLE_F2_FS)
+  {
+      ${OPC}      (op(OP_Branch) flags (CBR));
+  }
+
+  /* Integer Ialu operations, no flags needed */
+  $for (OPC in Lop_MOV Lop_ABS Lop_OR Lop_AND 
+               Lop_XOR Lop_NOR Lop_NAND Lop_NXOR      
+               Lop_OR_NOT Lop_AND_NOT Lop_OR_COMPL Lop_AND_COMPL 
+               Lop_LSL Lop_LSR Lop_ASR Lop_ADD
+               Lop_L_MAC Lop_L_MSU Lop_ADD_SAT Lop_ADD_SAT_U
+               Lop_SUB_SAT Lop_SUB_SAT_U
+               Lop_SAT Lop_SAT_U
+               Lop_ADD_U Lop_SUB Lop_SUB_U Lop_RCMP Lop_EQ
+               Lop_NE Lop_GT Lop_GT_U Lop_GE Lop_GE_U 
+               Lop_LT Lop_LT_U Lop_LE Lop_LE_U
+               Lop_SXT_C Lop_SXT_C2 Lop_SXT_I
+               Lop_ZXT_C Lop_ZXT_C2 Lop_ZXT_I
+	       Lop_EXTRACT_C Lop_EXTRACT_C2 Lop_EXTRACT Lop_EXTRACT_U Lop_DEPOSIT
+               Lop_LSLADD)
+  {
+      ${OPC}      (op(OP_IAlu));
+  }
+
+  /* Integer multiple operations, no flags needed.
+   * Simplified, treat multiply_add ops, etc same as multiply.
+   */
+  $for (OPC in Lop_MUL Lop_MUL_U Lop_MUL_ADD Lop_MUL_ADD_U Lop_MUL_SAT Lop_MUL_SAT_U
+               Lop_MUL_SUB Lop_MUL_SUB_U Lop_MUL_SUB_REV Lop_MUL_SUB_REV_U)
+  {
+      ${OPC}      (op(OP_IMul));
+  }
+
+  /* Integer divide operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_DIV Lop_DIV_U Lop_REM Lop_REM_U)
+  {
+      ${OPC}      (op(OP_IDiv) flags (EXCEPT));
+  }
+
+  /* Floating-point moves, cannot except */
+  Lop_MOV_F     (op(OP_FAlu));
+  Lop_MOV_F2    (op(OP_FAlu));
+
+  /* Floating-point alu operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_RCMP_F Lop_ABS_F Lop_ABS_F2 Lop_ADD_F Lop_ADD_F2
+               Lop_SUB_F Lop_SUB_F2 Lop_EQ_F Lop_EQ_F2
+               Lop_NE_F Lop_NE_F2 Lop_GT_F Lop_GT_F2
+               Lop_GE_F Lop_GE_F2 Lop_LT_F Lop_LT_F2
+               Lop_LE_F Lop_LE_F2 Lop_I_F Lop_F_I
+               Lop_I_F2 Lop_F2_I Lop_F_F2 Lop_F2_F)
+  {
+      ${OPC}      (op(OP_FAlu) flags (EXCEPT));
+  }
+
+  /* Floating-point multiple operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   * Simplified, treat multiply_add ops, etc same as multiply.
+   */
+  $for (OPC in Lop_MUL_F Lop_MUL_F2 Lop_MUL_ADD_F Lop_MUL_ADD_F2
+               Lop_MUL_SUB_F Lop_MUL_SUB_REV_F 
+               Lop_MUL_SUB_F2 Lop_MUL_SUB_REV_F2)
+  {
+      ${OPC}      (op(OP_FMul) flags (EXCEPT));
+  }
+
+  /* Floating-point divide operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   * Simplified, treat sqrt ops, etc same as divide.
+   */
+  $for (OPC in Lop_DIV_F Lop_DIV_F2 Lop_SQRT_F Lop_SQRT_F2)
+  {
+      ${OPC}      (op(OP_FDiv) flags (EXCEPT));
+  }
+
+  /* Loop over the possible data types for memory operations */
+  $for (TYPE in C C2 I Q F F2)
+  {
+    /* Load memory opcodes, must be marked with EXCEPT LOAD flag! 
+     * Will not speculate above branch unless one of the scheduling
+     * alternatives is a SILENT version.
+     * Pre and post increment loads (LD_PRE, LD_POST) are not currently 
+     * supported (as of IMPACT release 2.32).
+     */
+     Lop_LD_${TYPE} (op(OP_Load) flags (EXCEPT LOAD));
+
+
+    /* Store memory opcodes, must be marked with EXCEPT STORE flag! 
+     * Pre and post increment stores (ST_PRE, ST_POST) are not currently 
+     * supported (as of IMPACT release 2.32).
+     */
+     Lop_ST_${TYPE} (op(OP_Store) flags (EXCEPT STORE));
+  }
+
+  /* Unsigned character/short loads (there are no unsigned stores) */
+  Lop_LD_UC       (op(OP_Load) flags (EXCEPT LOAD));
+  Lop_LD_UC2      (op(OP_Load) flags (EXCEPT LOAD));
+  Lop_LD_UI       (op(OP_Load) flags (EXCEPT LOAD));
+
+  /* Predicate load/store operations */
+  Lop_PRED_LD     (op(OP_Load) flags(EXCEPT LOAD));
+  Lop_PRED_ST     (op(OP_Store) flags(EXCEPT STORE));
+
+  /* Load/store block of 32 predicate registers (used by register allocator) */
+  Lop_PRED_LD_BLK (op(OP_Load) flags(EXCEPT LOAD));
+  Lop_PRED_ST_BLK (op(OP_Store) flags(EXCEPT STORE));
+
+  /* PRED_CLEAR and PRED_SET clears/sets a single predicate, primarily for 
+   * the convenence of the compiler writer. They need to be folded into
+   * later predicate definitions (via optimizations) and the rest converted 
+   * into operations that set/clear multiple predicates (perhaps up to 32) 
+   * in a single operation.  Since these pred clear/set optimizations are
+   * not currently supported (as of IMPACT release 2.32), make an aggressive 
+   * assumption that they are free and ignore their cost by treating them 
+   * as compiler directives.  (The alternative, to treat them as regular 
+   * operations is way too conservative, since many of them can be folded 
+   * in with later predicate definitions (thus eliminated) and the rest
+   * can be converted into at least predicate definitions (which allow
+   * setting two predicates per operation).
+   */
+  Lop_PRED_CLEAR(op(OP_IAlu) flags(IGNORE));
+  Lop_PRED_SET  (op(OP_IAlu) flags(IGNORE));
+
+  /* Predicate definition opcodes using integer comparisons.
+   * No flags needed. 
+   */
+  $for (OPC in Lop_CMP Lop_PRED_EQ Lop_PRED_NE Lop_PRED_GT Lop_PRED_GT_U 
+               Lop_PRED_GE Lop_PRED_GE_U Lop_PRED_LT Lop_PRED_LT_U
+               Lop_PRED_LE Lop_PRED_LE_U Lop_PRED_COPY)
+  {
+      ${OPC}      (op(OP_IAlu));
+  }
+
+  /* Predicate definition opcodes using floating-point comparisons.
+   * EXCEPT flag must be specified. Will not speculate above branch
+   * unless one of the scheduling alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_CMP_F Lop_PRED_EQ_F2 Lop_PRED_NE_F2 Lop_PRED_GT_F2 Lop_PRED_GE_F2
+               Lop_PRED_LT_F2 Lop_PRED_LE_F2 Lop_PRED_EQ_F Lop_PRED_NE_F
+               Lop_PRED_GT_F Lop_PRED_GE_F Lop_PRED_LT_F Lop_PRED_LE_F)
+  {
+      ${OPC}      (op(OP_FAlu) flags (EXCEPT));
+  }
+}
+
+
+
diff -urN openimpact-1.0rc4/mdes/Limpact/IMPACT_GEN_BASE.hmdes openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_GEN_BASE.hmdes
--- openimpact-1.0rc4/mdes/Limpact/IMPACT_GEN_BASE.hmdes	1969-12-31 18:00:00.000000000 -0600
+++ openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_GEN_BASE.hmdes	2004-09-17 14:41:02.000000000 -0500
@@ -0,0 +1,647 @@
+Version1
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%%
+%%		      Illinois Open Source License
+%%                     University of Illinois/NCSA
+%%                         Open Source License
+%%
+%% Copyright (c) 2004, The University of Illinois at Urbana-Champaign.
+%% All rights reserved.
+%%
+%% Developed by:             
+%%
+%%		IMPACT Research Group
+%%
+%%		University of Illinois at Urbana-Champaign
+%%
+%%              http://www.crhc.uiuc.edu/IMPACT
+%%              http://www.gelato.org
+%%
+%% Permission is hereby granted, free of charge, to any person
+%% obtaining a copy of this software and associated documentation
+%% files (the "Software"), to deal with the Software without
+%% restriction, including without limitation the rights to use, copy,
+%% modify, merge, publish, distribute, sublicense, and/or sell copies
+%% of the Software, and to permit persons to whom the Software is
+%% furnished to do so, subject to the following conditions:
+%%
+%% Redistributions of source code must retain the above copyright
+%% notice, this list of conditions and the following disclaimers.
+%%
+%% Redistributions in binary form must reproduce the above copyright
+%% notice, this list of conditions and the following disclaimers in
+%% the documentation and/or other materials provided with the
+%% distribution.
+%%
+%% Neither the names of the IMPACT Research Group, the University of
+%% Illinois, nor the names of its contributors may be used to endorse
+%% or promote products derived from this Software without specific
+%% prior written permission.  THE SOFTWARE IS PROVIDED "AS IS",
+%% WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
+%% LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+%% PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+%% CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
+%% OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+%% OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+%% OR THE USE OR OTHER DEALINGS WITH THE SOFTWARE.
+%%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%
+% IMPACT v1.0 Architecture High-Level Machine Description
+% Issue 1, general percolation
+% Author: Scott A. Mahlke
+% Date:   6-93
+
+$define ISSUE	1
+$define BRANCH	1
+
+(Define declaration
+    C_header_file	"$IMPACT_ROOT$/include/Lcode/l_opc.h"
+    C_header_file	"$IMPACT_ROOT$/include/Lcode/l_flags.h"
+    C_header_file	"$IMPACT_ROOT$/include/Lcode/limpact_phase1.h"
+    C_header_file	"$IMPACT_ROOT$/include/machine/m_spec.h"
+    C_header_file	"$IMPACT_ROOT$/include/machine/m_impact.h"
+    predicates		1
+    dest_operands	2
+    dest_syncs		4	# Used to construct control/sync dependences
+    source_operands	4
+    src_syncs		4	# Used to construct control/sync dependences
+    processor_model     superscalar
+end)
+
+#
+# name ((capacity "static" "rotating") (width "size in bits"))
+#
+
+(Register_Files declaration
+    p       ((capacity 32 0) (width 32))
+    i	    ((capacity 64 0) (width 32))
+    f	    ((capacity 64 0) (width 32))
+    f2	    ((capacity 32 0) (width 64))
+    
+    # generic literal field  bit field for short loads/stores
+    Lit    ((capacity 0 0) (width 32))
+    
+    Label   ((capacity 0 0) (width 32))
+
+    NULL    ((capacity 0 0) (width 0))
+    
+end)
+
+#
+# name (reg_file1 ...)
+#
+
+(IO_Sets declaration
+    REG (p i f f2)
+    CON (Lit Label)
+    SOME (REG Lit Label)
+    ANY (REG Lit Label NULL)
+    RANY (REG NULL)
+    
+end)
+
+#
+# name (<predicate0 ...>[dest0 ...][src0 ...])
+#
+
+(IO_Items declaration
+    # Standard 3 operand instruction format
+    IOI_Std3 		(<RANY>[REG - ][SOME SOME - - ])
+    
+    # Standard 5 operand instruction format
+    IOI_Std5		(<RANY>[REG RANY][SOME SOME SOME -])
+
+    # Predicate clear
+    IOI_predclr		([REG -][- - - -])
+
+    # Predicate copy
+    IOI_predcopy	(<RANY>[REG -][- - - -])
+
+    # Predicate comparison
+    IOI_predcmp        (<RANY>[REG RANY][SOME SOME - - ])
+
+    # Operand format for "move"
+    IOI_mov 		(<RANY>[REG - ][SOME - - - ])
+    IOI_cmov		(<->   [REG - ][SOME SOME - -])
+    IOI_select		(<->   [REG - ][SOME SOME SOME -])
+
+    # Operand format for unconditional branch
+    # SAM 8/94 - 3 types of ubr, generic (ubr), predicated (pubr), 
+    #            non-predicated (npubr).  This is so can treat predicated
+    #            jumps just like conditional branches, but still handle other
+    #            unconditional brs like jrg and jsr separately
+    IOI_rts		(<RANY>[ - - ][ - - - -])
+    IOI_ubr	 	(<RANY>[ - - ][SOME ANY - - ])
+    IOI_npubr	 	(      [ - - ][SOME ANY - - ])
+    IOI_pubr	 	(<REG> [ - - ][SOME ANY - - ])
+   
+    # Operand format for conditional branch
+    IOI_cbr		(<RANY>[ - - ][SOME SOME CON - ])
+   
+    # Operand format for stores
+	# basic store
+    IOI_store1		(<RANY>[ - - ][SOME SOME SOME - ])
+    	# pre/post inc store
+    IOI_store2		(<RANY>[REG - ][SOME SOME SOME SOME ])
+
+    # Operand format for loads
+	# basic load
+    IOI_load1		(<RANY>[REG - ][SOME SOME - - ])
+    	# pre/post inc load
+    IOI_load2		(<RANY>[REG REG][SOME SOME SOME - ])
+
+    IOI_Nil 	(<RANY>[][])
+    IOI_Ch 	(<RANY>[][ANY ANY ANY])
+    IOI_Ignore  (<RANY>[ANY ANY][ANY ANY ANY ANY])
+end)
+
+# Enumerate resources
+
+(Resources declaration
+    slot[0..$ISSUE$]
+    ialu[0..$ISSUE$]
+    imul[0..$ISSUE$]
+    idiv[0..$ISSUE$]
+    fpalu[0..$ISSUE$]
+    fpmul[0..$ISSUE$]
+    fpdiv[0..$ISSUE$]
+    mem[0..$ISSUE$]
+    branch[0..$BRANCH$]
+end)
+
+(ResTables declaration
+    RL_INOP    ( # 1 cycle NOP
+    			(slot 0)
+	       )
+    RL_IAlu    ( # 1 cycle IAlu
+    			(slot 0)
+			(ialu 0)
+	       )
+    RL_IMul    ( # fully pipelined IMul
+			(slot 0)
+			(imul 0)
+	       )
+    RL_IDiv    ( # fully pipelined IDiv
+			(slot 0)
+			(idiv 0)
+	       )
+    RL_FPAlu   ( # fully pipelined single/double precision fp alu op 
+    			(slot 0)
+			(fpalu 0)
+	       )
+    RL_FPMul   ( # fully pipelined single/double precision fp multiply
+    			(slot 0)
+    			(fpmul 0)
+	       )
+    RL_FPDiv   ( # fully pipelined single/double precision fp divide
+    			(slot 0)
+    			(fpdiv 0)
+	       )
+    RL_Load    ( # fully pipelined load
+		 	(slot 0)
+			(mem 0)
+    	       )
+    RL_Store   ( # fully pipelined store
+    			(slot 0)
+			(mem  0)
+    	       )
+    RL_Branch  ( # fully pipelined branch
+			(slot 0)
+			(branch 0)
+               )
+end)
+
+
+# 
+# name (exception_latency (pred) (dest0 ...) (src0 ...) (sync_dest ...) (sync_src ...)
+#
+#       Sync arcs description   1: memory
+#                               2: control
+#                               3: synchronization
+#                               4: vliw (special use, set to 0)
+
+(Latencies declaration
+    Lat1    ( 1 (0) (1 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))
+    Lat1ma  ( 1 (0) (0 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# st
+    Lat1mb  ( 1 (0) (1 0) (0 0 0 0) (1 0 0 0) (0 0 0 0))	# post/pre inc st
+    Lat1ba  ( 1 (0) (1 0) (0 0 0 0) (0 1 0 0) (0 0 0 0))	# uncond branches
+    Lat1bb  ( 1 (0) (1 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# int cond branches
+    Lat1p   ( 1 (0) (1 1) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# int pred compares
+    Lat2ma  ( 2 (0) (2 0) (0 0 0 0) (1 0 0 0) (0 0 0 0))	# ld
+    Lat2mb  ( 2 (0) (2 1) (0 0 0 0) (1 0 0 0) (0 0 0 0))	# post/pre inc ld
+
+# Lat3's changed to 2 cycles to match HPPA :) SAM 9-94
+    Lat3    ( 2 (0) (2 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))
+    Lat3a   ( 2 (0) (2 2) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# mul_add, mul_sub
+    Lat3bb  ( 2 (0) (2 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# flt/dbl cond branches
+    Lat3p   ( 2 (0) (2 2) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# flt/dbl pred compares
+    Lat10   ( 10 (0) (10 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))
+end)
+    
+# name ((io_list, resource_list, latency) ...())
+(Operation_class declaration
+	CL_Ignore
+		(
+			(IOI_Ignore RL_INOP Lat1)
+		)
+end)
+
+# lcode_name <op_flags> (assembly_name <alt_flags> (operation_class))
+#
+# The following op_flags are supported:
+#       op_flags must be the same across common lcode_names
+#
+#       IGNORE - scheduler ignores this op
+#       CBR - conditional branch op
+#       JMP - unconditional branch op
+#       JSR - subroutine call
+#       RTS - subroutine return
+#       SYNC - synchronization op
+#       LOAD - load op
+#       STORE - store op
+#       EXCEPT - op may cause an exception
+#
+# The following alt_flags are supported:
+#       alternative flags may be different across common lcode_names
+#
+#       SILENT - speculative version
+
+(Operations declaration 
+
+# Lcode opcodes that are ignored by scheduler
+	Lop_DEFINE	<IGNORE>        (Lop_DEFINE	           CL_Ignore)
+	Lop_ALLOC	<IGNORE>        (Lop_ALLOC	           CL_Ignore)
+	Lop_EPILOGUE	<SYNC>          (Lop_EPILOGUE	           CL_Ignore)
+	Lop_PROLOGUE	<IGNORE>        (Lop_PROLOGUE	           CL_Ignore)
+	Lop_SIM_DIR	<IGNORE>        (Lop_SIM_DIR	           CL_Ignore)
+	Lop_BOUNDARY    <IGNORE>	(Lop_BOUNDARY              CL_Ignore)
+	
+# The remaining opcodes are supported by the scheduler
+	Lop_NO_OP   		        (Lop_NO_OP               ((IOI_Nil RL_INOP  Lat1)) )
+        Lop_CHECK       <CHK>   	(Lop_CHECK   		 ((IOI_Ch RL_INOP  Lat1)) )
+        Lop_CONFIRM     <CHK>   	(Lop_CONFIRM 		 ((IOI_Ch RL_INOP  Lat1)) )
+ 
+ 	Lop_JSR		<JSR> 	        (Lop_JSR                 ((IOI_ubr  RL_Branch  Lat1ba)) )
+ 	Lop_JSR_FS	<JSR> 	        (Lop_JSR_FS              ((IOI_ubr  RL_Branch  Lat1ba)) )
+
+    	Lop_RTS		<RTS>	        (Lop_RTS                 ((IOI_rts  RL_Branch  Lat1ba)) )
+    	Lop_RTS_FS	<RTS>	        (Lop_RTS_FS              ((IOI_rts  RL_Branch  Lat1ba)) )
+
+    	Lop_JUMP	<JMP>           (Lop_JUMP                ((IOI_npubr  RL_Branch  Lat1ba)) )
+    	Lop_JUMP	<JMP>           (Lop_JUMP                ((IOI_pubr  RL_Branch  Lat1bb)) )
+	Lop_JUMP_FS	<JMP> 	        (Lop_JUMP_FS             ((IOI_npubr  RL_Branch  Lat1ba)) )
+	Lop_JUMP_FS	<JMP> 	        (Lop_JUMP_FS             ((IOI_pubr  RL_Branch  Lat1bb)) )
+
+	Lop_JUMP_RG	<JMP>	        (Lop_JUMP_RG             ((IOI_ubr  RL_Branch  Lat1ba)) )
+      	Lop_JUMP_RG_FS	<JMP>	        (Lop_JUMP_RG_FS          ((IOI_ubr  RL_Branch  Lat1ba)) )
+
+# Conditional branch instructions
+
+	Lop_BEQ         <CBR>           (Lop_BEQ                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BEQ_FS      <CBR>           (Lop_BEQ_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BNE         <CBR>           (Lop_BNE                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BNE_FS      <CBR>           (Lop_BNE_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGT         <CBR>           (Lop_BGT                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGT_FS      <CBR>           (Lop_BGT_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE         <CBR>           (Lop_BGE                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE_FS      <CBR>           (Lop_BGE_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT         <CBR>           (Lop_BLT                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT_FS      <CBR>           (Lop_BLT_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE         <CBR>           (Lop_BLE                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE_FS      <CBR>           (Lop_BLE_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+
+	Lop_BGT_U       <CBR>           (Lop_BGT_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGT_U_FS    <CBR>           (Lop_BGT_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE_U       <CBR>           (Lop_BGE_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE_U_FS    <CBR>           (Lop_BGE_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT_U       <CBR>           (Lop_BLT_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT_U_FS    <CBR>           (Lop_BLT_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE_U       <CBR>           (Lop_BLE_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE_U_FS    <CBR>           (Lop_BLE_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+
+	Lop_BEQ_F       <CBR EXCEPT>    (Lop_BEQ_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BEQ_F_FS    <CBR EXCEPT>    (Lop_BEQ_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F       <CBR EXCEPT>    (Lop_BNE_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F_FS    <CBR EXCEPT>    (Lop_BNE_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F       <CBR EXCEPT>    (Lop_BGT_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F_FS    <CBR EXCEPT>    (Lop_BGT_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F       <CBR EXCEPT>    (Lop_BGE_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F_FS    <CBR EXCEPT>    (Lop_BGE_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F       <CBR EXCEPT>    (Lop_BLT_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F_FS    <CBR EXCEPT>    (Lop_BLT_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F       <CBR EXCEPT>    (Lop_BLE_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F_FS    <CBR EXCEPT>    (Lop_BLE_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+
+	Lop_BEQ_F2      <CBR EXCEPT>    (Lop_BEQ_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BEQ_F2_FS   <CBR EXCEPT>    (Lop_BEQ_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F2      <CBR EXCEPT>    (Lop_BNE_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F2_FS   <CBR EXCEPT>    (Lop_BNE_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F2      <CBR EXCEPT>    (Lop_BGT_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F2_FS   <CBR EXCEPT>    (Lop_BGT_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F2      <CBR EXCEPT>    (Lop_BGE_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F2_FS   <CBR EXCEPT>    (Lop_BGE_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F2      <CBR EXCEPT>    (Lop_BLT_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F2_FS   <CBR EXCEPT>    (Lop_BLT_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F2      <CBR EXCEPT>    (Lop_BLE_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F2_FS   <CBR EXCEPT>    (Lop_BLE_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+
+# Integer ALU instructions
+
+	Lop_MOV	                        (Lop_MOV                 ((IOI_mov RL_IAlu  Lat1)) )
+	Lop_ABS	                        (Lop_ABS                 ((IOI_mov RL_IAlu  Lat1)) )
+	
+    	Lop_OR	                        (Lop_OR                  ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_AND	                        (Lop_AND                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_XOR	                        (Lop_XOR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_NOR	                        (Lop_NOR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_NAND                        (Lop_NAND                ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_NXOR                        (Lop_NXOR                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_OR_NOT                      (Lop_OR_NOT              ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_AND_NOT                     (Lop_AND_NOT             ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_OR_COMPL                    (Lop_OR_COMPL            ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_AND_COMPL                   (Lop_AND_COMPL           ((IOI_Std3  RL_IAlu  Lat1)) )
+
+	Lop_LSL	                        (Lop_LSL                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_LSR	                        (Lop_LSR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_ASR	                        (Lop_ASR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+
+	Lop_ADD	                        (Lop_ADD                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_ADD_U                       (Lop_ADD_U               ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_SUB	                        (Lop_SUB                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_SUB_U                       (Lop_SUB_U               ((IOI_Std3  RL_IAlu  Lat1)) )
+	
+				    
+# Integer comparison instructions
+
+    	Lop_EQ	                        (Lop_EQ                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_NE	                        (Lop_NE                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GT	                        (Lop_GT                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GT_U                        (Lop_GT_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GE	                        (Lop_GE                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GE_U                        (Lop_GE_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LT	                        (Lop_LT                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LT_U                        (Lop_LT_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LE	                        (Lop_LE                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LE_U                        (Lop_LE_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+
+# Misc integer instructions
+
+	Lop_MUL	                        (Lop_MUL                 ((IOI_Std3  RL_IMul  Lat3)) )
+	Lop_MUL_U                       (Lop_MUL_U               ((IOI_Std3  RL_IMul  Lat3)) )
+	Lop_DIV	        <EXCEPT>        (Lop_DIV                 ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_DIV	        <EXCEPT>        (Lop_DIV         <SILENT>  ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_DIV_U       <EXCEPT>        (Lop_DIV_U               ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_DIV_U       <EXCEPT>        (Lop_DIV_U       <SILENT>  ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_REM	        <EXCEPT>        (Lop_REM                 ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_REM	        <EXCEPT>        (Lop_REM         <SILENT>  ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_REM_U       <EXCEPT>        (Lop_REM_U               ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_REM_U       <EXCEPT>        (Lop_REM_U       <SILENT>  ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_MUL_ADD                     (Lop_MUL_ADD             ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_ADD_U                   (Lop_MUL_ADD_U           ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB                     (Lop_MUL_SUB             ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB_U                   (Lop_MUL_SUB_U           ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB_REV                 (Lop_MUL_SUB_REV         ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB_REV_U               (Lop_MUL_SUB_REV_U       ((IOI_Std5  RL_IMul  Lat3)) )
+	
+# Floating point ALU instructions
+
+	Lop_MOV_F    		        (Lop_MOV_F               ((IOI_mov   RL_FPAlu  Lat1)) )
+	Lop_MOV_F2    		        (Lop_MOV_F2              ((IOI_mov   RL_FPAlu  Lat1)) )
+	Lop_ABS_F    	<EXCEPT>        (Lop_ABS_F               ((IOI_mov   RL_FPAlu  Lat1)) )
+	Lop_ABS_F    	<EXCEPT>        (Lop_ABS_F      <SILENT> ((IOI_mov   RL_FPAlu  Lat1)) )
+	Lop_ABS_F2    	<EXCEPT>        (Lop_ABS_F2              ((IOI_mov   RL_FPAlu  Lat1)) )
+	Lop_ABS_F2    	<EXCEPT>        (Lop_ABS_F2     <SILENT> ((IOI_mov   RL_FPAlu  Lat1)) )
+
+      	Lop_ADD_F       <EXCEPT>   	(Lop_ADD_F               ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_ADD_F       <EXCEPT>   	(Lop_ADD_F       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_ADD_F2      <EXCEPT>   	(Lop_ADD_F2              ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_ADD_F2      <EXCEPT>   	(Lop_ADD_F2      <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_SUB_F       <EXCEPT>   	(Lop_SUB_F               ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_SUB_F       <EXCEPT>   	(Lop_SUB_F       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_SUB_F2      <EXCEPT>   	(Lop_SUB_F2              ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_SUB_F2      <EXCEPT>   	(Lop_SUB_F2      <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+
+# Floating point comparison instructions
+
+	Lop_EQ_F        <EXCEPT>  	(Lop_EQ_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_EQ_F        <EXCEPT>  	(Lop_EQ_F        <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_EQ_F2       <EXCEPT>  	(Lop_EQ_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_EQ_F2       <EXCEPT>  	(Lop_EQ_F2       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_NE_F        <EXCEPT>  	(Lop_NE_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_NE_F        <EXCEPT>  	(Lop_NE_F        <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_NE_F2       <EXCEPT>  	(Lop_NE_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_NE_F2       <EXCEPT>  	(Lop_NE_F2       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GT_F        <EXCEPT>  	(Lop_GT_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GT_F        <EXCEPT>  	(Lop_GT_F        <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GT_F2       <EXCEPT>  	(Lop_GT_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GT_F2       <EXCEPT>  	(Lop_GT_F2       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GE_F        <EXCEPT>  	(Lop_GE_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GE_F        <EXCEPT>  	(Lop_GE_F        <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GE_F2       <EXCEPT>  	(Lop_GE_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GE_F2       <EXCEPT>  	(Lop_GE_F2       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LT_F        <EXCEPT>  	(Lop_LT_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LT_F        <EXCEPT>  	(Lop_LT_F        <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LT_F2       <EXCEPT>  	(Lop_LT_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LT_F2       <EXCEPT>  	(Lop_LT_F2       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LE_F        <EXCEPT>  	(Lop_LE_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LE_F        <EXCEPT>  	(Lop_LE_F        <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LE_F2       <EXCEPT>  	(Lop_LE_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LE_F2       <EXCEPT>  	(Lop_LE_F2       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+
+# Float point conversion instructions
+
+    	Lop_I_F	        <EXCEPT>	(Lop_I_F                 ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_I_F	        <EXCEPT>	(Lop_I_F         <SILENT>  ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F_I	        <EXCEPT>	(Lop_F_I                 ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F_I	        <EXCEPT>	(Lop_F_I         <SILENT>  ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_I_F2        <EXCEPT>	(Lop_I_F2                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_I_F2        <EXCEPT>	(Lop_I_F2        <SILENT>  ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F2_I        <EXCEPT>	(Lop_F2_I                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F2_I        <EXCEPT>	(Lop_F2_I        <SILENT>  ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F_F2        <EXCEPT>	(Lop_F_F2                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F_F2        <EXCEPT>	(Lop_F_F2        <SILENT>  ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F2_F        <EXCEPT>	(Lop_F2_F                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F2_F        <EXCEPT>	(Lop_F2_F        <SILENT>  ((IOI_mov   RL_FPAlu  Lat3)) )
+
+# Misc floating point instructions 
+
+	Lop_MUL_F       <EXCEPT>	(Lop_MUL_F          	 ((IOI_Std3  RL_FPMul  Lat3)) )
+	Lop_MUL_F       <EXCEPT>	(Lop_MUL_F       <SILENT>  ((IOI_Std3  RL_FPMul  Lat3)) )
+	Lop_MUL_F2      <EXCEPT>	(Lop_MUL_F2     	 ((IOI_Std3  RL_FPMul  Lat3)) )
+	Lop_MUL_F2      <EXCEPT>	(Lop_MUL_F2      <SILENT>  ((IOI_Std3  RL_FPMul  Lat3)) )
+	Lop_DIV_F       <EXCEPT>	(Lop_DIV_F	         ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_DIV_F       <EXCEPT>	(Lop_DIV_F       <SILENT>  ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_DIV_F2      <EXCEPT>	(Lop_DIV_F2	         ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_DIV_F2      <EXCEPT>	(Lop_DIV_F2      <SILENT>  ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_MUL_ADD_F   <EXCEPT>        (Lop_MUL_ADD_F	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_ADD_F   <EXCEPT>        (Lop_MUL_ADD_F   <SILENT>  ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_ADD_F2  <EXCEPT>        (Lop_MUL_ADD_F2	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_ADD_F2  <EXCEPT>        (Lop_MUL_ADD_F2	 <SILENT>  ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_F   <EXCEPT>        (Lop_MUL_SUB_F	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_F   <EXCEPT>        (Lop_MUL_SUB_F	 <SILENT>  ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_REV_F  <EXCEPT>     (Lop_MUL_SUB_REV_F       ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_REV_F  <EXCEPT>     (Lop_MUL_SUB_REV_F  <SILENT> ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_F2  <EXCEPT>        (Lop_MUL_SUB_F2	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_F2  <EXCEPT>        (Lop_MUL_SUB_F2	 <SILENT>  ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_REV_F2 <EXCEPT>     (Lop_MUL_SUB_REV_F2	 ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_REV_F2 <EXCEPT>     (Lop_MUL_SUB_REV_F2 <SILENT> ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_SQRT_F       <EXCEPT>	(Lop_SQRT_F	         ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_SQRT_F       <EXCEPT>	(Lop_SQRT_F	<SILENT> ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_SQRT_F2      <EXCEPT>	(Lop_SQRT_F2	         ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_SQRT_F2      <EXCEPT>	(Lop_SQRT_F2	<SILENT> ((IOI_Std3  RL_FPDiv  Lat10)) )
+	
+# Load instructions
+
+	Lop_LD_UC	<LOAD EXCEPT>	(Lop_LD_UC               ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_UC	<LOAD EXCEPT>	(Lop_LD_UC       <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_UC	<LOAD EXCEPT>	(Lop_LD_PRE_UC           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_UC	<LOAD EXCEPT>	(Lop_LD_PRE_UC   <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_UC	<LOAD EXCEPT>	(Lop_LD_POST_UC          ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_UC	<LOAD EXCEPT>	(Lop_LD_POST_UC  <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+
+	Lop_LD_C	<LOAD EXCEPT>	(Lop_LD_C                ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_C	<LOAD EXCEPT>	(Lop_LD_C        <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_C	<LOAD EXCEPT>	(Lop_LD_PRE_C            ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_C	<LOAD EXCEPT>	(Lop_LD_PRE_C    <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_C	<LOAD EXCEPT>	(Lop_LD_POST_C           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_C	<LOAD EXCEPT>	(Lop_LD_POST_C   <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_UC2	<LOAD EXCEPT>	(Lop_LD_UC2              ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_UC2	<LOAD EXCEPT>	(Lop_LD_UC2      <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_UC2	<LOAD EXCEPT>	(Lop_LD_PRE_UC2          ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_UC2	<LOAD EXCEPT>	(Lop_LD_PRE_UC2  <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_UC2	<LOAD EXCEPT>	(Lop_LD_POST_UC2         ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_UC2	<LOAD EXCEPT>	(Lop_LD_POST_UC2 <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+
+	Lop_LD_C2	<LOAD EXCEPT>	(Lop_LD_C2               ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_C2	<LOAD EXCEPT>	(Lop_LD_C2       <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_C2	<LOAD EXCEPT>	(Lop_LD_PRE_C2           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_C2	<LOAD EXCEPT>	(Lop_LD_PRE_C2   <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_C2	<LOAD EXCEPT>	(Lop_LD_POST_C2          ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_C2	<LOAD EXCEPT>	(Lop_LD_POST_C2  <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_I	<LOAD EXCEPT>	(Lop_LD_I                ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_I	<LOAD EXCEPT>	(Lop_LD_I        <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_I	<LOAD EXCEPT>	(Lop_LD_PRE_I            ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_I	<LOAD EXCEPT>	(Lop_LD_PRE_I    <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_I	<LOAD EXCEPT>	(Lop_LD_POST_I           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_I	<LOAD EXCEPT>	(Lop_LD_POST_I   <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_F	<LOAD EXCEPT>	(Lop_LD_F                ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_F	<LOAD EXCEPT>	(Lop_LD_F        <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_F	<LOAD EXCEPT>	(Lop_LD_PRE_F            ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_F	<LOAD EXCEPT>	(Lop_LD_PRE_F    <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_F	<LOAD EXCEPT>	(Lop_LD_POST_F           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_F	<LOAD EXCEPT>	(Lop_LD_POST_F   <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_F2	<LOAD EXCEPT>	(Lop_LD_F2               ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_F2	<LOAD EXCEPT>	(Lop_LD_F2       <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_F2	<LOAD EXCEPT>	(Lop_LD_PRE_F2           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_F2	<LOAD EXCEPT>	(Lop_LD_PRE_F2   <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_F2	<LOAD EXCEPT>	(Lop_LD_POST_F2          ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_F2	<LOAD EXCEPT>	(Lop_LD_POST_F2  <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	
+# Store instructions
+
+	Lop_ST_C	<STORE EXCEPT>	(Lop_ST_C                ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_C	<STORE EXCEPT>	(Lop_ST_C        <SILENT>  ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_C	<STORE EXCEPT>	(Lop_ST_PRE_C            ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_PRE_C	<STORE EXCEPT>	(Lop_ST_PRE_C    <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_C	<STORE EXCEPT>	(Lop_ST_POST_C           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_C	<STORE EXCEPT>	(Lop_ST_POST_C   <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_C2	<STORE EXCEPT>	(Lop_ST_C2               ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_C2	<STORE EXCEPT>	(Lop_ST_C2       <SILENT>  ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_C2	<STORE EXCEPT>	(Lop_ST_PRE_C2           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_PRE_C2	<STORE EXCEPT>	(Lop_ST_PRE_C2   <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_C2	<STORE EXCEPT>	(Lop_ST_POST_C2          ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_C2	<STORE EXCEPT>	(Lop_ST_POST_C2  <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_I	<STORE EXCEPT>	(Lop_ST_I                ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_I	<STORE EXCEPT>	(Lop_ST_I        <SILENT>  ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_I	<STORE EXCEPT>	(Lop_ST_PRE_I            ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_PRE_I	<STORE EXCEPT>	(Lop_ST_PRE_I    <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_I	<STORE EXCEPT>	(Lop_ST_POST_I           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_I	<STORE EXCEPT>	(Lop_ST_POST_I   <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_F	<STORE EXCEPT>	(Lop_ST_F                ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_F	<STORE EXCEPT>	(Lop_ST_F        <SILENT>  ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_F	<STORE EXCEPT>	(Lop_ST_PRE_F            ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_PRE_F	<STORE EXCEPT>	(Lop_ST_PRE_F    <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_F	<STORE EXCEPT>	(Lop_ST_POST_F           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_F	<STORE EXCEPT>	(Lop_ST_POST_F   <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_F2	<STORE EXCEPT>	(Lop_ST_F2               ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_F2	<STORE EXCEPT>	(Lop_ST_F2       <SILENT>  ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_F2	<STORE EXCEPT>	(Lop_ST_PRE_F2           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_PRE_F2	<STORE EXCEPT>	(Lop_ST_PRE_F2   <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_F2	<STORE EXCEPT>	(Lop_ST_POST_F2          ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_F2	<STORE EXCEPT>	(Lop_ST_POST_F2  <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+
+# Predicate setting instructions
+
+	Lop_PRED_CLEAR  <IGNORE>        (Lop_PRED_CLEAR		 ((IOI_predclr RL_IAlu Lat1)) )
+	Lop_PRED_SET    <IGNORE>        (Lop_PRED_SET		 ((IOI_predclr RL_IAlu Lat1)) )
+	Lop_PRED_COPY   (Lop_PRED_COPY		 ((IOI_predcopy RL_IAlu Lat1)) )
+
+	Lop_PRED_LD	<LOAD EXCEPT>	(Lop_PRED_LD		 ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_PRED_LD	<LOAD EXCEPT>	(Lop_PRED_LD	 <SILENT>	 ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_PRED_LD_BLK	<LOAD EXCEPT>	(Lop_PRED_LD_BLK	 ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_PRED_LD_BLK	<LOAD EXCEPT>	(Lop_PRED_LD_BLK <SILENT>	 ((IOI_load1 RL_Load Lat2ma)) )
+
+	Lop_PRED_ST	<STORE EXCEPT>	(Lop_PRED_ST		 ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_PRED_ST	<STORE EXCEPT>	(Lop_PRED_ST	 <SILENT>	 ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_PRED_ST_BLK	<STORE EXCEPT>	(Lop_PRED_ST_BLK	 ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_PRED_ST_BLK	<STORE EXCEPT>	(Lop_PRED_ST_BLK <SILENT>	 ((IOI_store1 RL_Store Lat1ma)) )
+
+	Lop_PRED_EQ			(Lop_PRED_EQ		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_NE			(Lop_PRED_NE		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GT			(Lop_PRED_GT		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GT_U			(Lop_PRED_GT_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GE			(Lop_PRED_GE		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GE_U			(Lop_PRED_GE_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LT			(Lop_PRED_LT		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LT_U			(Lop_PRED_LT_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LE			(Lop_PRED_LE		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LE_U			(Lop_PRED_LE_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+
+	Lop_PRED_EQ_F2	<EXCEPT>	(Lop_PRED_EQ_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_EQ_F2	<EXCEPT>	(Lop_PRED_EQ_F2	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_NE_F2	<EXCEPT>	(Lop_PRED_NE_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_NE_F2	<EXCEPT>	(Lop_PRED_NE_F2	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GT_F2	<EXCEPT>	(Lop_PRED_GT_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GT_F2	<EXCEPT>	(Lop_PRED_GT_F2	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GE_F2	<EXCEPT>	(Lop_PRED_GE_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GE_F2	<EXCEPT>	(Lop_PRED_GE_F2	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LT_F2	<EXCEPT>	(Lop_PRED_LT_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LT_F2	<EXCEPT>	(Lop_PRED_LT_F2	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LE_F2	<EXCEPT>	(Lop_PRED_LE_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LE_F2	<EXCEPT>	(Lop_PRED_LE_F2	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+
+	Lop_PRED_EQ_F	<EXCEPT>	(Lop_PRED_EQ_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_EQ_F	<EXCEPT>	(Lop_PRED_EQ_F	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_NE_F	<EXCEPT>	(Lop_PRED_NE_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_NE_F	<EXCEPT>	(Lop_PRED_NE_F	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GT_F	<EXCEPT>	(Lop_PRED_GT_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GT_F	<EXCEPT>	(Lop_PRED_GT_F	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GE_F	<EXCEPT>	(Lop_PRED_GE_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GE_F	<EXCEPT>	(Lop_PRED_GE_F	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LT_F	<EXCEPT>	(Lop_PRED_LT_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LT_F	<EXCEPT>	(Lop_PRED_LT_F	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LE_F	<EXCEPT>	(Lop_PRED_LE_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LE_F	<EXCEPT>	(Lop_PRED_LE_F	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+
+	Lop_CMOV			(Lop_CMOV		 ((IOI_cmov RL_IAlu  Lat1)) )
+	Lop_CMOV_COM			(Lop_CMOV_COM		 ((IOI_cmov RL_IAlu  Lat1)) )
+	Lop_CMOV_F			(Lop_CMOV_F		 ((IOI_cmov RL_FPAlu Lat1)) )
+	Lop_CMOV_COM_F			(Lop_CMOV_COM_F		 ((IOI_cmov RL_FPAlu Lat1)) )
+	Lop_CMOV_F2			(Lop_CMOV_F2		 ((IOI_cmov RL_FPAlu Lat1)) )
+	Lop_CMOV_COM_F2			(Lop_CMOV_COM_F2	 ((IOI_cmov RL_FPAlu Lat1)) )
+
+	Lop_SELECT			(Lop_SELECT		 ((IOI_select RL_IAlu  Lat1)) )
+	Lop_SELECT_F			(Lop_SELECT_F		 ((IOI_select RL_FPAlu Lat1)) )
+	Lop_SELECT_F2			(Lop_SELECT_F2		 ((IOI_select RL_FPAlu Lat1)) )
+
+end)
diff -urN openimpact-1.0rc4/mdes/Limpact/IMPACT_GEN_NEWPRED_BASE.hmdes openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_GEN_NEWPRED_BASE.hmdes
--- openimpact-1.0rc4/mdes/Limpact/IMPACT_GEN_NEWPRED_BASE.hmdes	1969-12-31 18:00:00.000000000 -0600
+++ openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_GEN_NEWPRED_BASE.hmdes	2004-09-17 14:41:03.000000000 -0500
@@ -0,0 +1,652 @@
+Version1
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%%
+%%		      Illinois Open Source License
+%%                     University of Illinois/NCSA
+%%                         Open Source License
+%%
+%% Copyright (c) 2004, The University of Illinois at Urbana-Champaign.
+%% All rights reserved.
+%%
+%% Developed by:             
+%%
+%%		IMPACT Research Group
+%%
+%%		University of Illinois at Urbana-Champaign
+%%
+%%              http://www.crhc.uiuc.edu/IMPACT
+%%              http://www.gelato.org
+%%
+%% Permission is hereby granted, free of charge, to any person
+%% obtaining a copy of this software and associated documentation
+%% files (the "Software"), to deal with the Software without
+%% restriction, including without limitation the rights to use, copy,
+%% modify, merge, publish, distribute, sublicense, and/or sell copies
+%% of the Software, and to permit persons to whom the Software is
+%% furnished to do so, subject to the following conditions:
+%%
+%% Redistributions of source code must retain the above copyright
+%% notice, this list of conditions and the following disclaimers.
+%%
+%% Redistributions in binary form must reproduce the above copyright
+%% notice, this list of conditions and the following disclaimers in
+%% the documentation and/or other materials provided with the
+%% distribution.
+%%
+%% Neither the names of the IMPACT Research Group, the University of
+%% Illinois, nor the names of its contributors may be used to endorse
+%% or promote products derived from this Software without specific
+%% prior written permission.  THE SOFTWARE IS PROVIDED "AS IS",
+%% WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
+%% LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+%% PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+%% CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
+%% OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+%% OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+%% OR THE USE OR OTHER DEALINGS WITH THE SOFTWARE.
+%%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% IMPACT v1.0 Architecture High-Level Machine Description
+% Issue 1, general percolation
+% Author: Scott A. Mahlke
+% Date:   6-93
+
+$define ISSUE	1
+$define BRANCH	1
+
+(Define declaration
+    C_header_file	"$IMPACT_ROOT$/include/Lcode/l_opc.h"
+    C_header_file	"$IMPACT_ROOT$/include/Lcode/l_flags.h"
+    C_header_file	"$IMPACT_ROOT$/include/Lcode/limpact_phase1.h"
+    C_header_file	"$IMPACT_ROOT$/include/machine/m_spec.h"
+    C_header_file	"$IMPACT_ROOT$/include/machine/m_impact.h"
+    predicates		1
+    dest_operands	16
+    dest_syncs		4	# Used to construct control/sync dependences
+    source_operands	16
+    src_syncs		4	# Used to construct control/sync dependences
+    processor_model     superscalar
+end)
+
+#
+# name ((capacity "static" "rotating") (width "size in bits"))
+#
+
+(Register_Files declaration
+    p       ((capacity 32 0) (width 32))
+    i	    ((capacity 64 0) (width 32))
+    f	    ((capacity 64 0) (width 32))
+    f2	    ((capacity 32 0) (width 64))
+    
+    # generic literal field  bit field for short loads/stores
+    Lit    ((capacity 0 0) (width 32))
+    
+    Label   ((capacity 0 0) (width 32))
+
+    NULL    ((capacity 0 0) (width 0))
+    
+end)
+
+#
+# name (reg_file1 ...)
+#
+
+(IO_Sets declaration
+    REG (p i f f2)
+    CON (Lit Label)
+    SOME (REG Lit Label)
+    ANY (REG Lit Label NULL)
+    RANY (REG NULL)
+    
+end)
+
+#
+# name (<predicate0 ...>[dest0 ...][src0 ...])
+#
+
+(IO_Items declaration
+    # Standard 3 operand instruction format
+    IOI_Std3 		(<RANY>[REG - ][SOME SOME - - ])
+    
+    # Standard 5 operand instruction format
+    IOI_Std5		(<RANY>[REG RANY][SOME SOME SOME -])
+
+    # Predicate clear
+    IOI_predclr		([REG -][- - - -])
+
+    # Predicate copy
+    IOI_predcopy	(<RANY>[REG -][- - - -])
+
+    # Predicate comparison
+    IOI_predcmp        (<RANY>[REG RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY][SOME SOME - - ])
+
+    IOI_pred_mask_combine    (<RANY>[REG - ][REG RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY ])
+
+    # Operand format for "move"
+    IOI_mov 		(<RANY>[REG - ][SOME - - - ])
+    IOI_cmov		(<->   [REG - ][SOME SOME - -])
+    IOI_select		(<->   [REG - ][SOME SOME SOME -])
+
+    # Operand format for unconditional branch
+    # SAM 8/94 - 3 types of ubr, generic (ubr), predicated (pubr), 
+    #            non-predicated (npubr).  This is so can treat predicated
+    #            jumps just like conditional branches, but still handle other
+    #            unconditional brs like jrg and jsr separately
+    IOI_rts		(<RANY>[ - - ][ - - - -])
+    IOI_ubr	 	(<RANY>[ - - ][SOME ANY - - ])
+    IOI_npubr	 	(      [ - - ][SOME ANY - - ])
+    IOI_pubr	 	(<REG> [ - - ][SOME ANY - - ])
+   
+    # Operand format for conditional branch
+    IOI_cbr		(<RANY>[ - - ][SOME SOME CON - ])
+   
+    # Operand format for stores
+	# basic store
+    IOI_store1		(<RANY>[ - - ][SOME SOME SOME - ])
+    	# pre/post inc store
+    IOI_store2		(<RANY>[REG - ][SOME SOME SOME SOME ])
+
+    # Operand format for loads
+	# basic load
+    IOI_load1		(<RANY>[REG - ][SOME SOME - - ])
+    	# pre/post inc load
+    IOI_load2		(<RANY>[REG REG][SOME SOME SOME - ])
+
+    IOI_Nil 	(<RANY>[][])
+    IOI_Ch 	(<RANY>[][ANY ANY ANY])
+    IOI_Ignore  (<RANY>[ANY ANY][ANY ANY ANY ANY])
+end)
+
+# Enumerate resources
+
+(Resources declaration
+    slot[0..$ISSUE$]
+    ialu[0..$ISSUE$]
+    imul[0..$ISSUE$]
+    idiv[0..$ISSUE$]
+    fpalu[0..$ISSUE$]
+    fpmul[0..$ISSUE$]
+    fpdiv[0..$ISSUE$]
+    mem[0..$ISSUE$]
+    branch[0..$BRANCH$]
+end)
+
+(ResTables declaration
+    RL_INOP    ( # 1 cycle NOP
+    			(slot 0)
+	       )
+    RL_IAlu    ( # 1 cycle IAlu
+    			(slot 0)
+			(ialu 0)
+	       )
+    RL_IMul    ( # fully pipelined IMul
+			(slot 0)
+			(imul 0)
+	       )
+    RL_IDiv    ( # fully pipelined IDiv
+			(slot 0)
+			(idiv 0)
+	       )
+    RL_FPAlu   ( # fully pipelined single/double precision fp alu op 
+    			(slot 0)
+			(fpalu 0)
+	       )
+    RL_FPMul   ( # fully pipelined single/double precision fp multiply
+    			(slot 0)
+    			(fpmul 0)
+	       )
+    RL_FPDiv   ( # fully pipelined single/double precision fp divide
+    			(slot 0)
+    			(fpdiv 0)
+	       )
+    RL_Load    ( # fully pipelined load
+		 	(slot 0)
+			(mem 0)
+    	       )
+    RL_Store   ( # fully pipelined store
+    			(slot 0)
+			(mem  0)
+    	       )
+    RL_Branch  ( # fully pipelined branch
+			(slot 0)
+			(branch 0)
+               )
+end)
+
+
+# 
+# name (exception_latency (pred) (dest0 ...) (src0 ...) (sync_dest ...) (sync_src ...)
+#
+#       Sync arcs description   1: memory
+#                               2: control
+#                               3: synchronization
+#                               4: vliw (special use, set to 0)
+
+(Latencies declaration
+    Lat0pc  ( 0 (0) (0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 0) (0 0 0 0))
+    Lat1    ( 1 (0) (1 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))
+    Lat1ma  ( 1 (0) (0 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# st
+    Lat1mb  ( 1 (0) (1 0) (0 0 0 0) (1 0 0 0) (0 0 0 0))	# post/pre inc st
+    Lat1ba  ( 1 (0) (1 0) (0 0 0 0) (0 1 0 0) (0 0 0 0))	# uncond branches
+    Lat1bb  ( 1 (0) (1 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# int cond branches
+    Lat1p   ( 1 (0) (1 1) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# int pred compares
+    Lat2ma  ( 2 (0) (2 0) (0 0 0 0) (1 0 0 0) (0 0 0 0))	# ld
+    Lat2mb  ( 2 (0) (2 1) (0 0 0 0) (1 0 0 0) (0 0 0 0))	# post/pre inc ld
+
+# Lat3's changed to 2 cycles to match HPPA :) SAM 9-94
+    Lat3    ( 2 (0) (2 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))
+    Lat3a   ( 2 (0) (2 2) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# mul_add, mul_sub
+    Lat3bb  ( 2 (0) (2 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# flt/dbl cond branches
+    Lat3p   ( 2 (0) (2 2) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# flt/dbl pred compares
+    Lat10   ( 10 (0) (10 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))
+end)
+    
+# name ((io_list, resource_list, latency) ...())
+(Operation_class declaration
+	CL_Ignore
+		(
+			(IOI_Ignore RL_INOP Lat1)
+		)
+end)
+
+# lcode_name <op_flags> (assembly_name <alt_flags> (operation_class))
+#
+# The following op_flags are supported:
+#       op_flags must be the same across common lcode_names
+#
+#       IGNORE - scheduler ignores this op
+#       CBR - conditional branch op
+#       JMP - unconditional branch op
+#       JSR - subroutine call
+#       RTS - subroutine return
+#       SYNC - synchronization op
+#       LOAD - load op
+#       STORE - store op
+#       EXCEPT - op may cause an exception
+#
+# The following alt_flags are supported:
+#       alternative flags may be different across common lcode_names
+#
+#       SILENT - speculative version
+
+(Operations declaration 
+
+# Lcode opcodes that are ignored by scheduler
+	Lop_DEFINE	<IGNORE>        (Lop_DEFINE	           CL_Ignore)
+	Lop_ALLOC	<IGNORE>        (Lop_ALLOC	           CL_Ignore)
+	Lop_EPILOGUE	<SYNC>          (Lop_EPILOGUE	           CL_Ignore)
+	Lop_PROLOGUE	<IGNORE>        (Lop_PROLOGUE	           CL_Ignore)
+	Lop_SIM_DIR	<IGNORE>        (Lop_SIM_DIR	           CL_Ignore)
+	Lop_BOUNDARY    <IGNORE>	(Lop_BOUNDARY              CL_Ignore)
+	
+# The remaining opcodes are supported by the scheduler
+	Lop_NO_OP   		        (Lop_NO_OP               ((IOI_Nil RL_INOP  Lat1)) )
+        Lop_CHECK       <CHK>   	(Lop_CHECK   		 ((IOI_Ch RL_INOP  Lat1)) )
+        Lop_CONFIRM     <CHK>   	(Lop_CONFIRM 		 ((IOI_Ch RL_INOP  Lat1)) )
+ 
+ 	Lop_JSR		<JSR> 	        (Lop_JSR                 ((IOI_ubr  RL_Branch  Lat1ba)) )
+ 	Lop_JSR_FS	<JSR> 	        (Lop_JSR_FS              ((IOI_ubr  RL_Branch  Lat1ba)) )
+
+    	Lop_RTS		<RTS>	        (Lop_RTS                 ((IOI_rts  RL_Branch  Lat1ba)) )
+    	Lop_RTS_FS	<RTS>	        (Lop_RTS_FS              ((IOI_rts  RL_Branch  Lat1ba)) )
+
+    	Lop_JUMP	<JMP>           (Lop_JUMP                ((IOI_npubr  RL_Branch  Lat1ba)) )
+    	Lop_JUMP	<JMP>           (Lop_JUMP                ((IOI_pubr  RL_Branch  Lat1bb)) )
+	Lop_JUMP_FS	<JMP> 	        (Lop_JUMP_FS             ((IOI_npubr  RL_Branch  Lat1ba)) )
+	Lop_JUMP_FS	<JMP> 	        (Lop_JUMP_FS             ((IOI_pubr  RL_Branch  Lat1bb)) )
+
+	Lop_JUMP_RG	<JMP>	        (Lop_JUMP_RG             ((IOI_ubr  RL_Branch  Lat1ba)) )
+      	Lop_JUMP_RG_FS	<JMP>	        (Lop_JUMP_RG_FS          ((IOI_ubr  RL_Branch  Lat1ba)) )
+
+# Conditional branch instructions
+
+	Lop_BEQ         <CBR>           (Lop_BEQ                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BEQ_FS      <CBR>           (Lop_BEQ_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BNE         <CBR>           (Lop_BNE                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BNE_FS      <CBR>           (Lop_BNE_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGT         <CBR>           (Lop_BGT                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGT_FS      <CBR>           (Lop_BGT_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE         <CBR>           (Lop_BGE                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE_FS      <CBR>           (Lop_BGE_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT         <CBR>           (Lop_BLT                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT_FS      <CBR>           (Lop_BLT_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE         <CBR>           (Lop_BLE                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE_FS      <CBR>           (Lop_BLE_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+
+	Lop_BGT_U       <CBR>           (Lop_BGT_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGT_U_FS    <CBR>           (Lop_BGT_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE_U       <CBR>           (Lop_BGE_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE_U_FS    <CBR>           (Lop_BGE_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT_U       <CBR>           (Lop_BLT_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT_U_FS    <CBR>           (Lop_BLT_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE_U       <CBR>           (Lop_BLE_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE_U_FS    <CBR>           (Lop_BLE_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+
+	Lop_BEQ_F       <CBR EXCEPT>    (Lop_BEQ_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BEQ_F_FS    <CBR EXCEPT>    (Lop_BEQ_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F       <CBR EXCEPT>    (Lop_BNE_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F_FS    <CBR EXCEPT>    (Lop_BNE_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F       <CBR EXCEPT>    (Lop_BGT_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F_FS    <CBR EXCEPT>    (Lop_BGT_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F       <CBR EXCEPT>    (Lop_BGE_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F_FS    <CBR EXCEPT>    (Lop_BGE_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F       <CBR EXCEPT>    (Lop_BLT_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F_FS    <CBR EXCEPT>    (Lop_BLT_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F       <CBR EXCEPT>    (Lop_BLE_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F_FS    <CBR EXCEPT>    (Lop_BLE_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+
+	Lop_BEQ_F2      <CBR EXCEPT>    (Lop_BEQ_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BEQ_F2_FS   <CBR EXCEPT>    (Lop_BEQ_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F2      <CBR EXCEPT>    (Lop_BNE_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F2_FS   <CBR EXCEPT>    (Lop_BNE_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F2      <CBR EXCEPT>    (Lop_BGT_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F2_FS   <CBR EXCEPT>    (Lop_BGT_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F2      <CBR EXCEPT>    (Lop_BGE_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F2_FS   <CBR EXCEPT>    (Lop_BGE_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F2      <CBR EXCEPT>    (Lop_BLT_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F2_FS   <CBR EXCEPT>    (Lop_BLT_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F2      <CBR EXCEPT>    (Lop_BLE_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F2_FS   <CBR EXCEPT>    (Lop_BLE_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+
+# Integer ALU instructions
+
+	Lop_MOV	                        (Lop_MOV                 ((IOI_mov RL_IAlu  Lat1)) )
+	Lop_ABS	                        (Lop_ABS                 ((IOI_mov RL_IAlu  Lat1)) )
+	
+    	Lop_OR	                        (Lop_OR                  ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_AND	                        (Lop_AND                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_XOR	                        (Lop_XOR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_NOR	                        (Lop_NOR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_NAND                        (Lop_NAND                ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_NXOR                        (Lop_NXOR                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_OR_NOT                      (Lop_OR_NOT              ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_AND_NOT                     (Lop_AND_NOT             ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_OR_COMPL                    (Lop_OR_COMPL            ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_AND_COMPL                   (Lop_AND_COMPL           ((IOI_Std3  RL_IAlu  Lat1)) )
+
+	Lop_LSL	                        (Lop_LSL                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_LSR	                        (Lop_LSR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_ASR	                        (Lop_ASR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+
+	Lop_ADD	                        (Lop_ADD                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_ADD_U                       (Lop_ADD_U               ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_SUB	                        (Lop_SUB                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_SUB_U                       (Lop_SUB_U               ((IOI_Std3  RL_IAlu  Lat1)) )
+	
+				    
+# Integer comparison instructions
+
+    	Lop_EQ	                        (Lop_EQ                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_NE	                        (Lop_NE                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GT	                        (Lop_GT                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GT_U                        (Lop_GT_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GE	                        (Lop_GE                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GE_U                        (Lop_GE_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LT	                        (Lop_LT                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LT_U                        (Lop_LT_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LE	                        (Lop_LE                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LE_U                        (Lop_LE_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+
+# Misc integer instructions
+
+	Lop_MUL	                        (Lop_MUL                 ((IOI_Std3  RL_IMul  Lat3)) )
+	Lop_MUL_U                       (Lop_MUL_U               ((IOI_Std3  RL_IMul  Lat3)) )
+	Lop_DIV	        <EXCEPT>        (Lop_DIV                 ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_DIV	        <EXCEPT>        (Lop_DIV         <SILENT>  ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_DIV_U       <EXCEPT>        (Lop_DIV_U               ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_DIV_U       <EXCEPT>        (Lop_DIV_U       <SILENT>  ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_REM	        <EXCEPT>        (Lop_REM                 ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_REM	        <EXCEPT>        (Lop_REM         <SILENT>  ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_REM_U       <EXCEPT>        (Lop_REM_U               ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_REM_U       <EXCEPT>        (Lop_REM_U       <SILENT>  ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_MUL_ADD                     (Lop_MUL_ADD             ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_ADD_U                   (Lop_MUL_ADD_U           ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB                     (Lop_MUL_SUB             ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB_U                   (Lop_MUL_SUB_U           ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB_REV                 (Lop_MUL_SUB_REV         ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB_REV_U               (Lop_MUL_SUB_REV_U       ((IOI_Std5  RL_IMul  Lat3)) )
+	
+# Floating point ALU instructions
+
+	Lop_MOV_F    		        (Lop_MOV_F               ((IOI_mov   RL_FPAlu  Lat1)) )
+	Lop_MOV_F2    		        (Lop_MOV_F2              ((IOI_mov   RL_FPAlu  Lat1)) )
+	Lop_ABS_F    	<EXCEPT>        (Lop_ABS_F               ((IOI_mov   RL_FPAlu  Lat1)) )
+	Lop_ABS_F    	<EXCEPT>        (Lop_ABS_F      <SILENT> ((IOI_mov   RL_FPAlu  Lat1)) )
+	Lop_ABS_F2    	<EXCEPT>        (Lop_ABS_F2              ((IOI_mov   RL_FPAlu  Lat1)) )
+	Lop_ABS_F2    	<EXCEPT>        (Lop_ABS_F2     <SILENT> ((IOI_mov   RL_FPAlu  Lat1)) )
+
+      	Lop_ADD_F       <EXCEPT>   	(Lop_ADD_F               ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_ADD_F       <EXCEPT>   	(Lop_ADD_F       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_ADD_F2      <EXCEPT>   	(Lop_ADD_F2              ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_ADD_F2      <EXCEPT>   	(Lop_ADD_F2      <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_SUB_F       <EXCEPT>   	(Lop_SUB_F               ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_SUB_F       <EXCEPT>   	(Lop_SUB_F       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_SUB_F2      <EXCEPT>   	(Lop_SUB_F2              ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_SUB_F2      <EXCEPT>   	(Lop_SUB_F2      <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+
+# Floating point comparison instructions
+
+	Lop_EQ_F        <EXCEPT>  	(Lop_EQ_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_EQ_F        <EXCEPT>  	(Lop_EQ_F        <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_EQ_F2       <EXCEPT>  	(Lop_EQ_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_EQ_F2       <EXCEPT>  	(Lop_EQ_F2       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_NE_F        <EXCEPT>  	(Lop_NE_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_NE_F        <EXCEPT>  	(Lop_NE_F        <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_NE_F2       <EXCEPT>  	(Lop_NE_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_NE_F2       <EXCEPT>  	(Lop_NE_F2       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GT_F        <EXCEPT>  	(Lop_GT_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GT_F        <EXCEPT>  	(Lop_GT_F        <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GT_F2       <EXCEPT>  	(Lop_GT_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GT_F2       <EXCEPT>  	(Lop_GT_F2       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GE_F        <EXCEPT>  	(Lop_GE_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GE_F        <EXCEPT>  	(Lop_GE_F        <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GE_F2       <EXCEPT>  	(Lop_GE_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GE_F2       <EXCEPT>  	(Lop_GE_F2       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LT_F        <EXCEPT>  	(Lop_LT_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LT_F        <EXCEPT>  	(Lop_LT_F        <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LT_F2       <EXCEPT>  	(Lop_LT_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LT_F2       <EXCEPT>  	(Lop_LT_F2       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LE_F        <EXCEPT>  	(Lop_LE_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LE_F        <EXCEPT>  	(Lop_LE_F        <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LE_F2       <EXCEPT>  	(Lop_LE_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LE_F2       <EXCEPT>  	(Lop_LE_F2       <SILENT>  ((IOI_Std3  RL_FPAlu  Lat3)) )
+
+# Float point conversion instructions
+
+    	Lop_I_F	        <EXCEPT>	(Lop_I_F                 ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_I_F	        <EXCEPT>	(Lop_I_F         <SILENT>  ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F_I	        <EXCEPT>	(Lop_F_I                 ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F_I	        <EXCEPT>	(Lop_F_I         <SILENT>  ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_I_F2        <EXCEPT>	(Lop_I_F2                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_I_F2        <EXCEPT>	(Lop_I_F2        <SILENT>  ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F2_I        <EXCEPT>	(Lop_F2_I                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F2_I        <EXCEPT>	(Lop_F2_I        <SILENT>  ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F_F2        <EXCEPT>	(Lop_F_F2                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F_F2        <EXCEPT>	(Lop_F_F2        <SILENT>  ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F2_F        <EXCEPT>	(Lop_F2_F                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F2_F        <EXCEPT>	(Lop_F2_F        <SILENT>  ((IOI_mov   RL_FPAlu  Lat3)) )
+
+# Misc floating point instructions 
+
+	Lop_MUL_F       <EXCEPT>	(Lop_MUL_F          	 ((IOI_Std3  RL_FPMul  Lat3)) )
+	Lop_MUL_F       <EXCEPT>	(Lop_MUL_F       <SILENT>  ((IOI_Std3  RL_FPMul  Lat3)) )
+	Lop_MUL_F2      <EXCEPT>	(Lop_MUL_F2     	 ((IOI_Std3  RL_FPMul  Lat3)) )
+	Lop_MUL_F2      <EXCEPT>	(Lop_MUL_F2      <SILENT>  ((IOI_Std3  RL_FPMul  Lat3)) )
+	Lop_DIV_F       <EXCEPT>	(Lop_DIV_F	         ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_DIV_F       <EXCEPT>	(Lop_DIV_F       <SILENT>  ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_DIV_F2      <EXCEPT>	(Lop_DIV_F2	         ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_DIV_F2      <EXCEPT>	(Lop_DIV_F2      <SILENT>  ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_MUL_ADD_F   <EXCEPT>        (Lop_MUL_ADD_F	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_ADD_F   <EXCEPT>        (Lop_MUL_ADD_F   <SILENT>  ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_ADD_F2  <EXCEPT>        (Lop_MUL_ADD_F2	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_ADD_F2  <EXCEPT>        (Lop_MUL_ADD_F2	 <SILENT>  ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_F   <EXCEPT>        (Lop_MUL_SUB_F	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_F   <EXCEPT>        (Lop_MUL_SUB_F	 <SILENT>  ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_REV_F  <EXCEPT>     (Lop_MUL_SUB_REV_F       ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_REV_F  <EXCEPT>     (Lop_MUL_SUB_REV_F  <SILENT> ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_F2  <EXCEPT>        (Lop_MUL_SUB_F2	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_F2  <EXCEPT>        (Lop_MUL_SUB_F2	 <SILENT>  ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_REV_F2 <EXCEPT>     (Lop_MUL_SUB_REV_F2	 ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_REV_F2 <EXCEPT>     (Lop_MUL_SUB_REV_F2 <SILENT> ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_SQRT_F       <EXCEPT>	(Lop_SQRT_F	         ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_SQRT_F       <EXCEPT>	(Lop_SQRT_F	<SILENT> ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_SQRT_F2      <EXCEPT>	(Lop_SQRT_F2	         ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_SQRT_F2      <EXCEPT>	(Lop_SQRT_F2	<SILENT> ((IOI_Std3  RL_FPDiv  Lat10)) )
+	
+# Load instructions
+
+	Lop_LD_UC	<LOAD EXCEPT>	(Lop_LD_UC               ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_UC	<LOAD EXCEPT>	(Lop_LD_UC       <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_UC	<LOAD EXCEPT>	(Lop_LD_PRE_UC           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_UC	<LOAD EXCEPT>	(Lop_LD_PRE_UC   <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_UC	<LOAD EXCEPT>	(Lop_LD_POST_UC          ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_UC	<LOAD EXCEPT>	(Lop_LD_POST_UC  <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+
+	Lop_LD_C	<LOAD EXCEPT>	(Lop_LD_C                ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_C	<LOAD EXCEPT>	(Lop_LD_C        <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_C	<LOAD EXCEPT>	(Lop_LD_PRE_C            ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_C	<LOAD EXCEPT>	(Lop_LD_PRE_C    <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_C	<LOAD EXCEPT>	(Lop_LD_POST_C           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_C	<LOAD EXCEPT>	(Lop_LD_POST_C   <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_UC2	<LOAD EXCEPT>	(Lop_LD_UC2              ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_UC2	<LOAD EXCEPT>	(Lop_LD_UC2      <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_UC2	<LOAD EXCEPT>	(Lop_LD_PRE_UC2          ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_UC2	<LOAD EXCEPT>	(Lop_LD_PRE_UC2  <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_UC2	<LOAD EXCEPT>	(Lop_LD_POST_UC2         ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_UC2	<LOAD EXCEPT>	(Lop_LD_POST_UC2 <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+
+	Lop_LD_C2	<LOAD EXCEPT>	(Lop_LD_C2               ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_C2	<LOAD EXCEPT>	(Lop_LD_C2       <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_C2	<LOAD EXCEPT>	(Lop_LD_PRE_C2           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_C2	<LOAD EXCEPT>	(Lop_LD_PRE_C2   <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_C2	<LOAD EXCEPT>	(Lop_LD_POST_C2          ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_C2	<LOAD EXCEPT>	(Lop_LD_POST_C2  <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_I	<LOAD EXCEPT>	(Lop_LD_I                ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_I	<LOAD EXCEPT>	(Lop_LD_I        <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_I	<LOAD EXCEPT>	(Lop_LD_PRE_I            ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_I	<LOAD EXCEPT>	(Lop_LD_PRE_I    <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_I	<LOAD EXCEPT>	(Lop_LD_POST_I           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_I	<LOAD EXCEPT>	(Lop_LD_POST_I   <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_F	<LOAD EXCEPT>	(Lop_LD_F                ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_F	<LOAD EXCEPT>	(Lop_LD_F        <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_F	<LOAD EXCEPT>	(Lop_LD_PRE_F            ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_F	<LOAD EXCEPT>	(Lop_LD_PRE_F    <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_F	<LOAD EXCEPT>	(Lop_LD_POST_F           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_F	<LOAD EXCEPT>	(Lop_LD_POST_F   <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_F2	<LOAD EXCEPT>	(Lop_LD_F2               ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_F2	<LOAD EXCEPT>	(Lop_LD_F2       <SILENT>  ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_F2	<LOAD EXCEPT>	(Lop_LD_PRE_F2           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_PRE_F2	<LOAD EXCEPT>	(Lop_LD_PRE_F2   <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_F2	<LOAD EXCEPT>	(Lop_LD_POST_F2          ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_F2	<LOAD EXCEPT>	(Lop_LD_POST_F2  <SILENT>  ((IOI_load2 RL_Load Lat2mb)) )
+	
+# Store instructions
+
+	Lop_ST_C	<STORE EXCEPT>	(Lop_ST_C                ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_C	<STORE EXCEPT>	(Lop_ST_C        <SILENT>  ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_C	<STORE EXCEPT>	(Lop_ST_PRE_C            ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_PRE_C	<STORE EXCEPT>	(Lop_ST_PRE_C    <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_C	<STORE EXCEPT>	(Lop_ST_POST_C           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_C	<STORE EXCEPT>	(Lop_ST_POST_C   <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_C2	<STORE EXCEPT>	(Lop_ST_C2               ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_C2	<STORE EXCEPT>	(Lop_ST_C2       <SILENT>  ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_C2	<STORE EXCEPT>	(Lop_ST_PRE_C2           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_PRE_C2	<STORE EXCEPT>	(Lop_ST_PRE_C2   <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_C2	<STORE EXCEPT>	(Lop_ST_POST_C2          ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_C2	<STORE EXCEPT>	(Lop_ST_POST_C2  <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_I	<STORE EXCEPT>	(Lop_ST_I                ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_I	<STORE EXCEPT>	(Lop_ST_I        <SILENT>  ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_I	<STORE EXCEPT>	(Lop_ST_PRE_I            ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_PRE_I	<STORE EXCEPT>	(Lop_ST_PRE_I    <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_I	<STORE EXCEPT>	(Lop_ST_POST_I           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_I	<STORE EXCEPT>	(Lop_ST_POST_I   <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_F	<STORE EXCEPT>	(Lop_ST_F                ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_F	<STORE EXCEPT>	(Lop_ST_F        <SILENT>  ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_F	<STORE EXCEPT>	(Lop_ST_PRE_F            ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_PRE_F	<STORE EXCEPT>	(Lop_ST_PRE_F    <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_F	<STORE EXCEPT>	(Lop_ST_POST_F           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_F	<STORE EXCEPT>	(Lop_ST_POST_F   <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_F2	<STORE EXCEPT>	(Lop_ST_F2               ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_F2	<STORE EXCEPT>	(Lop_ST_F2       <SILENT>  ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_F2	<STORE EXCEPT>	(Lop_ST_PRE_F2           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_PRE_F2	<STORE EXCEPT>	(Lop_ST_PRE_F2   <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_F2	<STORE EXCEPT>	(Lop_ST_POST_F2          ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_F2	<STORE EXCEPT>	(Lop_ST_POST_F2  <SILENT>  ((IOI_store2 RL_Store Lat1mb)) )
+
+# Predicate setting instructions
+
+	Lop_PRED_CLEAR  <IGNORE>        (Lop_PRED_CLEAR		 ((IOI_predclr RL_IAlu Lat1)) )
+	Lop_PRED_SET    <IGNORE>        (Lop_PRED_SET		 ((IOI_predclr RL_IAlu Lat1)) )
+	Lop_PRED_COPY   (Lop_PRED_COPY		 ((IOI_predcopy RL_IAlu Lat1)) )
+
+	Lop_PRED_LD	<LOAD EXCEPT>	(Lop_PRED_LD		 ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_PRED_LD	<LOAD EXCEPT>	(Lop_PRED_LD	 <SILENT>	 ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_PRED_LD_BLK	<LOAD EXCEPT>	(Lop_PRED_LD_BLK	 ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_PRED_LD_BLK	<LOAD EXCEPT>	(Lop_PRED_LD_BLK <SILENT>	 ((IOI_load1 RL_Load Lat2ma)) )
+
+	Lop_PRED_ST	<STORE EXCEPT>	(Lop_PRED_ST		 ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_PRED_ST	<STORE EXCEPT>	(Lop_PRED_ST	 <SILENT>	 ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_PRED_ST_BLK	<STORE EXCEPT>	(Lop_PRED_ST_BLK	 ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_PRED_ST_BLK	<STORE EXCEPT>	(Lop_PRED_ST_BLK <SILENT>	 ((IOI_store1 RL_Store Lat1ma)) )
+
+	Lop_PRED_EQ			(Lop_PRED_EQ		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_NE			(Lop_PRED_NE		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GT			(Lop_PRED_GT		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GT_U			(Lop_PRED_GT_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GE			(Lop_PRED_GE		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GE_U			(Lop_PRED_GE_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LT			(Lop_PRED_LT		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LT_U			(Lop_PRED_LT_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LE			(Lop_PRED_LE		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LE_U			(Lop_PRED_LE_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+
+	Lop_PRED_EQ_F2	<EXCEPT>	(Lop_PRED_EQ_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_EQ_F2	<EXCEPT>	(Lop_PRED_EQ_F2	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_NE_F2	<EXCEPT>	(Lop_PRED_NE_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_NE_F2	<EXCEPT>	(Lop_PRED_NE_F2	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GT_F2	<EXCEPT>	(Lop_PRED_GT_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GT_F2	<EXCEPT>	(Lop_PRED_GT_F2	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GE_F2	<EXCEPT>	(Lop_PRED_GE_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GE_F2	<EXCEPT>	(Lop_PRED_GE_F2	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LT_F2	<EXCEPT>	(Lop_PRED_LT_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LT_F2	<EXCEPT>	(Lop_PRED_LT_F2	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LE_F2	<EXCEPT>	(Lop_PRED_LE_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LE_F2	<EXCEPT>	(Lop_PRED_LE_F2	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+
+	Lop_PRED_EQ_F	<EXCEPT>	(Lop_PRED_EQ_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_EQ_F	<EXCEPT>	(Lop_PRED_EQ_F	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_NE_F	<EXCEPT>	(Lop_PRED_NE_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_NE_F	<EXCEPT>	(Lop_PRED_NE_F	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GT_F	<EXCEPT>	(Lop_PRED_GT_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GT_F	<EXCEPT>	(Lop_PRED_GT_F	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GE_F	<EXCEPT>	(Lop_PRED_GE_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GE_F	<EXCEPT>	(Lop_PRED_GE_F	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LT_F	<EXCEPT>	(Lop_PRED_LT_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LT_F	<EXCEPT>	(Lop_PRED_LT_F	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LE_F	<EXCEPT>	(Lop_PRED_LE_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LE_F	<EXCEPT>	(Lop_PRED_LE_F	 <SILENT>	 ((IOI_predcmp RL_FPAlu Lat3p)) )
+
+	Lop_PRED_MASK_AND  		(Lop_PRED_MASK_AND	 ((IOI_pred_mask_combine RL_INOP Lat0pc)) )
+	Lop_PRED_MASK_OR  		(Lop_PRED_MASK_OR	 ((IOI_pred_mask_combine RL_INOP Lat0pc)) )
+
+	Lop_CMOV			(Lop_CMOV		 ((IOI_cmov RL_IAlu  Lat1)) )
+	Lop_CMOV_COM			(Lop_CMOV_COM		 ((IOI_cmov RL_IAlu  Lat1)) )
+	Lop_CMOV_F			(Lop_CMOV_F		 ((IOI_cmov RL_FPAlu Lat1)) )
+	Lop_CMOV_COM_F			(Lop_CMOV_COM_F		 ((IOI_cmov RL_FPAlu Lat1)) )
+	Lop_CMOV_F2			(Lop_CMOV_F2		 ((IOI_cmov RL_FPAlu Lat1)) )
+	Lop_CMOV_COM_F2			(Lop_CMOV_COM_F2	 ((IOI_cmov RL_FPAlu Lat1)) )
+
+	Lop_SELECT			(Lop_SELECT		 ((IOI_select RL_IAlu  Lat1)) )
+	Lop_SELECT_F			(Lop_SELECT_F		 ((IOI_select RL_FPAlu Lat1)) )
+	Lop_SELECT_F2			(Lop_SELECT_F2		 ((IOI_select RL_FPAlu Lat1)) )
+
+end)
diff -urN openimpact-1.0rc4/mdes/Limpact/IMPACT_IA64_TEMPLATE.hmdes2 openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_IA64_TEMPLATE.hmdes2
--- openimpact-1.0rc4/mdes/Limpact/IMPACT_IA64_TEMPLATE.hmdes2	1969-12-31 18:00:00.000000000 -0600
+++ openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_IA64_TEMPLATE.hmdes2	2004-09-17 14:41:03.000000000 -0500
@@ -0,0 +1,819 @@
+/*****************************************************************************\
+ *
+ *		      Illinois Open Source License
+ *                     University of Illinois/NCSA
+ *                         Open Source License
+ *
+ * Copyright (c) 2004, The University of Illinois at Urbana-Champaign.
+ * All rights reserved.
+ *
+ * Developed by:             
+ *
+ *		IMPACT Research Group
+ *
+ *		University of Illinois at Urbana-Champaign
+ *
+ *              http://www.crhc.uiuc.edu/IMPACT
+ *              http://www.gelato.org
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal with the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimers.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimers in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the names of the IMPACT Research Group, the University of
+ * Illinois, nor the names of its contributors may be used to endorse
+ * or promote products derived from this Software without specific
+ * prior written permission.  THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
+ * LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+ * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS WITH THE SOFTWARE.
+ *
+\*****************************************************************************/
+/* pseudo-ia64 IMPACT template */
+
+/* Read in the IMPACT's expected structure for this .hmdes2 file */
+$include "${IMPACT_REL_PATH}/mdes/structure/structure_IMPACT.hmdes2"
+
+/* 
+ * Processor resource configuration parameters. 
+ */
+
+$def WIDTH              6
+$def NUM_M_UNITS        2
+$def NUM_I_UNITS        2
+$def NUM_F_UNITS        2
+$def NUM_B_UNITS        3
+
+/*
+ * Cycle in which UBR / CBR load source predicate.  Setting to 1 instead
+ * of 0 yields a 0-cycle-delay between pred defines and branches.
+ */
+$def PBDELAY            1
+
+/* 
+ * Processor issue-rule configuration parameters. 
+ */
+$def BRANCHES_AT_END    1  // If 1, places branches at end of each instr packet
+$def NON_TRAPPING_OPS   1  // If 1, allow general speculation
+
+
+/* 
+ * Scheduling 'slots' are used by the scheduler to determine ordering of 
+ * operations within an operation packet (operations scheduled to execute 
+ * in the same cycle).  The 'decoder' resources are used by this machine
+ * description to set the maximum number of operations that can be issued 
+ * per cycle (WIDTH).  The 'branch' resources are used by this
+ * machine description to set the maximum number of branches that can
+ * be issued per cycle (NUM_B_UNITS).
+ *
+ * If there are no constraints on operation ordering within the packet
+ * (i.e., branches can be scheduled anywhere), we will create the same
+ * number of slots as decoders.  
+ *
+ *   Example SS_3G_2BX (3-issue, 2 branches anywhere):
+ *          slot0: any operation (branch or non-branch)
+ *          slot1: any operation 
+ *          slot2: any operation 
+ *       decoder1: any operation
+ *       decoder2: any operation
+ *       decoder3: any operation
+ *        branch1: any branch
+ *        branch2: any branch
+ *
+ *
+ * If branches must be placed at the end, but there is only one branch,
+ * we still create the same number of slots as decoders and just
+ * require branches to use the last slot.
+ *
+ *   Example SS_3G_1BL (3-issue, 1 branch last):
+ *          slot0: non-branch operation 
+ *          slot1: non-branch operation 
+ *          slot2: any operation 
+ *       decoder1: any operation
+ *       decoder2: any operation
+ *       decoder3: any operation
+ *        branch1: any branch
+ *
+ * If branches must be placed at the end, but there are more than one branch,
+ * we need to create more slots than decoders, in order to force branches
+ * to the end.  Although there are more slots in this case, the decoders
+ * still limit the operations per cycle (to WIDTH).
+ *
+ *   Example SS_3G_2BL (3-issue, 2 branches last):
+ *          slot0: non-branch operation   <- add1
+ *          slot1: non-branch operation   <- (not used)
+ *          slot2: any operation          <- branch1
+ *          slot3: branch operation       <- branch2
+ *       decoder1: any operation          <- add1
+ *       decoder2: any operation          <- branch1
+ *       decoder3: any operation          <- branch2
+ *        branch1: any branch             <- branch1
+ *        branch2: any branch             <- branch2
+ *
+ *  Example of why using the same number of slots does not work for SS_3G_2BL:
+ *          slot0: non-branch operation   <- add1
+ *          slot1: any operation          <- branch1
+ *          slot2: any operation          <- add2    (*not allowed*)
+ *       decoder1: any operation          <- add1
+ *       decoder2: any operation          <- branch1
+ *       decoder3: any operation          <- add2
+ *        branch1: any branch             <- branch1
+ *        branch2: any branch             <- (not used)
+ * 
+ * In the SS_3G_2BL example, it is *still* a three issue processor even
+ * though it has four issue slots!
+ *
+ * For historical reasons, the scheduler tools expect the slots to be
+ * numbered slot0,...slotN.
+ */
+$if (${BRANCHES_AT_END} == 1)
+{
+    /* Create the minimum number of slots that allow us to force
+     * branches to the end of the operation packet.
+     */
+    $def LAST_SLOT $={ (${WIDTH}-1) + (${NUM_B_UNITS}-1) }
+}
+$else
+{
+    /* Otherwise, just create one slot per decoder */
+    $def LAST_SLOT $={${WIDTH}-1}
+}
+
+
+/* Section for passing parameters to IMPACT's scheduler and 
+ * lmdes2_customizer 
+ */
+SECTION Parameter
+{
+  /* Used by lmdes2_customizer to assign integer numbers to many of the
+   * strings in this machine description, such as Lop_ADD, Label, REG
+   * EXCEPT, LOAD, etc.
+   */
+  customization_headers
+                (value("${IMPACT_ROOT}/include/Lcode/l_opc.h"
+                       "${IMPACT_ROOT}/include/Lcode/l_flags.h"
+                       "${IMPACT_ROOT}/include/Lcode/limpact_phase1.h"
+                       "${IMPACT_ROOT}/include/machine/m_spec.h"
+                       "${IMPACT_ROOT}/include/machine/m_impact.h"));
+
+  /* Phased out in version 2.31, but should always be set to "superscalar" 
+   * for backward compatibilty and so lmdes2_customizer does not complain.
+   * It is OK to set this to superscalar when targeting an EPIC processor!
+   */
+  processor_model (value("superscalar"));
+
+}
+
+/* Convert the scheduler operand types (NULL, p, i, f, f2, Label, and Lit)
+ * into the short name (A) that will be used to describe 
+ * the operation format mapping entries in Operation_Format.
+ */
+SECTION Field_Type
+{
+  /* Names the scheduler (thru Mspec) will use to describe the operands */
+  NULL ();                              // No operand allowed
+  p ();                                 // Predicate register operand 
+  i ();                                 // Integer register operand 
+  f ();                                 // Float register operand 
+  f2 ();                                // Double register operand 
+  Label ();                             // Generic label literal
+  Lit ();			        // Generic non-label literal
+  REG (compatible_with (i f f2));      // Generic register operand
+
+  /* Remap and group the names above into one letter names for ease of use 
+   * below in Operation Format.  Since not modeling register port usage
+   * in this template, just map everything to 'A'.
+   */
+  A (compatible_with (NULL p i f f2 Label Lit REG)); // Anything allowed
+}
+
+/* Define all the operation formats supported in the target machine.
+ *
+ * All entrys are in the form:
+ *   P0_D0D1_S0S1S2  
+ *
+ * where:
+ *   P0       is the pred[0] operand specifier 
+ *   D0       is the dest[0] operand specifier 
+ *   D1       is the dest[1] operand specifier 
+ *   S0       is the src[0] operand specifier 
+ *   S1       is the src[1] operand specifier 
+ *   S2       is the src[2] operand specifier 
+ *   
+ * Since in this template, we are not modeling register port usage, only
+ * one operation format is needed (significantly simplifying the rest of
+ * the machine description).
+ */
+SECTION Operation_Format
+{
+  A_AA_AAA                       (pred (A) dest (A A) src (A A A));
+}
+
+
+/*
+ *  Declare the processor resources that we wish to model.
+ *
+ *  Note: The resource names (such as decoder1) are *not* keywords.
+ *        Renaming all the resources to r1, r2, r3... r30 (and 
+ *        their references) will yield the exact same schedule.
+ *
+ *  Note: You can use as many or few resources as desired in order
+ *        to model the processor's execution constraints.  Typically,
+ *        we don't model anything that doesn't add execution constraints
+ *        (e.g., pipeline stages in fully-pipelined function units, etc.).
+ *         
+ *
+ *  Note: The 'slot' field is used to associate slot ids with particular
+ *        resource names.  For simplicity, we assign slot id 0, to slot0,
+ *        etc.  Not defining the 'slot' field indicates that this is 
+ *        a non-slot (i.e., normal) resource.
+ *        For example, to associate scheduler slot 3, with resource 
+ *        'my_slot_3':
+ *           my_slot_3 (slot(3));
+ */
+SECTION Resource
+{
+  /* Slots are used to control how operations are scheduled within the
+   * same cycle (instruction packet).  For historical reasons, slots
+   * are numbered starting from 0 (the first slot in the packet).
+   */
+  $for (I in $0..${LAST_SLOT})
+  {
+      slot${I} (slot(${I}));
+  }
+
+  /* Decoders are used to limit the number of operations that can
+   * issue in one cycle.
+   */
+  $for (I in $1..${WIDTH})
+  {
+      decoder${I} ();
+  }
+
+  /* Create the various functional units for this machine
+   * Note: All these units are assumed to be fully pipelined, so
+   *       we only need to model the first stage.
+   */
+  $for (I in $1..${NUM_I_UNITS})
+  {
+      ialu${I} ();
+  }
+
+  $for (I in $1..${NUM_F_UNITS})
+  {
+      falu${I} ();
+  }
+
+  $for (I in $1..${NUM_B_UNITS})
+  {
+      branch${I} ();
+  }
+
+  $for (I in $1..${NUM_M_UNITS})
+  {
+      mem${I} ();
+  }
+}
+
+/*
+ * Specify the possible times in the pipeline the resources can be 
+ * used.  Here is the time mapping used in this machine description
+ * for resource usages:
+ * 
+ *   0 -> Fetch stage
+ *   1 -> Decode stage
+ *   2 -> First execution stage
+ *   3 -> Second execution stage and write-back stage for latency 1 ops
+ *   4 -> Third execution stage and write-back stage for latency 2 ops
+ *   etc.
+ */
+SECTION Resource_Usage
+{
+
+  /*
+   * Fetch stage
+   */    
+  $for (I in $0..${LAST_SLOT})
+  {
+      RU_slot${I}_t0_0 (use(slot${I}) time (0));
+  }
+
+
+  /*
+   * Decoder stage
+   */
+  $for (I in $1..${WIDTH})
+  {
+      RU_decoder${I}_t1_1 (use(decoder${I}) time (1));
+  }
+
+
+  /*
+   * First execution stage
+   */
+  $for (I in $1..${NUM_I_UNITS})
+  {
+      RU_i_unit${I}_t2_2 (use(ialu${I}) time (2));
+  }
+
+  $for (I in $1..${NUM_F_UNITS})
+  {
+      RU_f_unit${I}_t2_2 (use(falu${I}) time (2));
+  }
+
+  $for (I in $1..${NUM_B_UNITS})
+  {
+      RU_b_unit${I}_t2_2 (use(branch${I}) time (2));
+  }
+
+  $for (I in $1..${NUM_M_UNITS})
+  {
+      RU_m_unit${I}_t2_2 (use(mem${I}) time (2));
+  }
+
+  /*
+   * Second execution stage and write-back stage for latency 1 ops
+   * etc.
+   */
+  /*
+   * We are assuming fully-pipelined functional units, so later
+   * stages do not need to be modeled.  We are not modeling register
+   * ports, so the write-backs don't need to be modeled.
+   */
+}
+
+/* Group together resource usages that should always be used together.
+ * None necessary for this simplified machine description.
+ */
+SECTION Resource_Unit
+{ 
+}
+
+/* Create options where any one of the options may be selected.
+ * For example, any one of the declared IALUs may be used.
+ *
+ * Note: Table options are used to create the OR part of AND/OR-trees.
+ */
+SECTION Table_Option
+{
+  /* Use any "normal" slot for non-branch operations. */
+  any_normal_slot_t0_0 
+  (
+      one_of($for (I in $0..(${WIDTH}-1)) {RU_slot${I}_t0_0 })
+  );
+
+  /* If placing branches at end, branches can only use the last normal
+   * slot and the extra slots after the normal slots (if 2 or more branches).
+   */
+  $if (${BRANCHES_AT_END} == 1)
+  {
+      any_branch_slot_t0_0
+      (
+          one_of($for (I in $(${WIDTH}-1)..${LAST_SLOT}){RU_slot${I}_t0_0 })
+      );
+  }
+  /* Otherwise, can place branch in any normal slot, just like non-branch ops*/
+  $else
+  {
+      any_branch_slot_t0_0 
+      (
+          one_of($for (I in $0..(${WIDTH}-1)) {RU_slot${I}_t0_0 })
+      );
+  }
+
+  /* 
+   * Allow any of the decoders to be used. 
+   * This resource use limits the processor's issue width, not slots.
+   */
+  any_decoder_t1_1 
+  (
+      one_of($for (I in $1..${WIDTH}){RU_decoder${I}_t1_1 })
+  );
+
+  /* 
+   * Allow any of the declared functional units to be used 
+   */
+  any_ialu_t2_2 
+  (
+      one_of($for (I in $1..${NUM_I_UNITS}) {RU_i_unit${I}_t2_2 })
+  );
+
+  any_falu_t2_2 
+  (
+      one_of($for (I in $1..${NUM_F_UNITS}) {RU_f_unit${I}_t2_2 })
+  );
+
+  any_mem_t2_2 
+  (
+      one_of($for (I in $1..${NUM_M_UNITS}) {RU_m_unit${I}_t2_2 })
+  );
+
+  any_im_t2_2
+  (
+      one_of($for (I in $1..${NUM_I_UNITS}) {RU_i_unit${I}_t2_2 }
+	     $for (I in $1..${NUM_M_UNITS}) {RU_m_unit${I}_t2_2 })
+  );
+
+  any_branch_t2_2 
+  (
+      one_of($for (I in $1..${NUM_B_UNITS}) {RU_b_unit${I}_t2_2 })
+  );
+}
+
+/* Create the AND-OR trees that describes the how the processor resources
+ * are used as the operation executes.  This is the AND part of the
+ * AND/OR-tree representation for reservation tables.
+ *
+ * Any mixture of Table_Option, Resource_Unit, and Resource Usage entries
+ * may be specified in the 'use' field.
+ */
+SECTION Reservation_Table
+{
+  /* Simplifying assumption, ialu can execute all integer operations */
+  RL_IAlu       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_ialu_t2_2));
+  RL_AAlu       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_im_t2_2));
+  RL_IMul       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_ialu_t2_2));
+  RL_IDiv       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_ialu_t2_2));
+  RL_INOP       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_ialu_t2_2));
+
+  /* Simplifying assumption, falu can execute all floating-point operations */
+  RL_FAlu       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_falu_t2_2));
+  RL_FMul       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_falu_t2_2));
+  RL_FDiv       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_falu_t2_2));
+
+  /* Simplifying assumption, mem unit can execute all memory operations */
+  RL_Load       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_mem_t2_2));
+  RL_Store      (use(any_normal_slot_t0_0 any_decoder_t1_1 any_mem_t2_2));
+
+  /* Branches use branch slots (set above based on branch placement rules) 
+   * but otherwise act like normal operations.
+   */
+  RL_Branch     (use(any_branch_slot_t0_0 any_decoder_t1_1 any_branch_t2_2));
+  RL_JSR        (use(any_branch_slot_t0_0 any_decoder_t1_1 any_branch_t2_2));
+}
+
+/* Declare all the times that operands (s0, d1, etc) can be read/written to.
+ * These are used to determine register flow dependence latencies.
+ * 
+ * "Sync" operands (ss0, sd0, etc.) are used to determine memory, control, 
+ * and synchronization flow dependence latencies.
+ */
+SECTION Operand_Latency
+{
+  /* Declare all the times source operands can be read.
+   * Time 0 (for latencies) is assumed to be just before the first
+   * execution stage (when most source operands are read).
+   */
+  $for (I in 0 1) 
+  {
+      s${I}       (time(${I}));
+      p${I}       (time(${I}));
+  }
+
+  /* Declare all the times destination operands can be written to.
+   * Given the above assumption, this should be set to the operation latency.
+   * (Since the flow-dependence distance with be (dest_lat - src_lat).
+   */
+  $def LATENCIES {1 2 3 5 15}
+  $for (I in ${LATENCIES}) 
+  {
+      d${I}       (time(${I}));
+  }
+
+  /* Declare all the times sync source operands can be read. */
+  $for (I in 0) 
+  {
+      ss${I}      (time(${I}));
+  }
+
+  /* Declare all the times sync dest operands can be written to. */
+  $for (I in 0) 
+  {
+      sd${I}      (time(${I}));
+  }
+}
+
+/* Declare all the operation latency combinations allowed.
+ * The flow-dependence distance between two operands are determined
+ * with (dest_lat - src_lat).  So if dest_lat = 2, and src_lat = 0,
+ * a flow dependence with a two-cycle latency will be added.
+ */
+SECTION Operation_Latency
+{
+  /* Simplifying assumption, assume all sources are read at time 0, and
+   * destinations are written at their latency.  Assume all flow dependences
+   * between dependent memory and branch operations are 0 cycles.
+   */  
+  $for (I in ${LATENCIES}) 
+  {
+      Lat${I}     (dest(d${I} d${I})
+                   src(s0 s0 s0)
+                   pred(p0)
+                   mem_dest(sd0)
+                   ctrl_dest(sd0)
+                   sync_dest(sd0)
+                   mem_src(ss0)
+                   ctrl_src(ss0)
+                   sync_src(ss0));               
+  }
+
+  LatDP1	(dest(d1 d1)
+                 src(s0 s0 s0)
+                 pred(p${PBDELAY})
+                 mem_dest(sd0)
+                 ctrl_dest(sd0)
+                 sync_dest(sd0)
+                 mem_src(ss0)
+                 ctrl_src(ss0)
+                 sync_src(ss0));	
+
+}
+
+/* This section's entries group together an operation format, 
+ * reservation table,and an operation latency entry. 
+ * The requirements for all three entries need to be met in order for 
+ * the operation to be scheduled.
+ *
+ * Since we can model all the resource usage options with a single 
+ * AND/OR-tree-based reservation table and we have only one operation 
+ * format, we need only one scheduling alternative per operation type 
+ * to model resource constraints.
+ *
+ * However, if general speculation is enabled, create silent versions
+ * of operations that can except.
+ */
+SECTION Scheduling_Alternative
+{
+  ALT_IAlu     (format(A_AA_AAA) resv (RL_IAlu) latency(Lat1));
+  ALT_AAlu     (format(A_AA_AAA) resv (RL_AAlu) latency(Lat1));
+  ALT_IMul     (format(A_AA_AAA) resv (RL_FAlu) latency(Lat5));
+  ALT_IDiv     (format(A_AA_AAA) resv (RL_FAlu) latency(Lat5));
+  ALT_INOP     (format(A_AA_AAA) resv (RL_IAlu) latency(Lat1));
+  ALT_FAlu     (format(A_AA_AAA) resv (RL_FAlu) latency(Lat5));
+  ALT_FMul     (format(A_AA_AAA) resv (RL_FAlu) latency(Lat5));
+  ALT_FDiv     (format(A_AA_AAA) resv (RL_FAlu) latency(Lat15));
+  ALT_Load     (format(A_AA_AAA) resv (RL_Load) latency(Lat2));
+  ALT_Store    (format(A_AA_AAA) resv (RL_Store) latency(Lat1));
+  ALT_Branch   (format(A_AA_AAA) resv (RL_Branch) latency(LatDP1));
+  ALT_JSR      (format(A_AA_AAA) resv (RL_JSR) latency(Lat1));
+
+  /* Create silent versions of operations if non-trapping operations
+   * are specified as being supported.
+   */
+  $if(${NON_TRAPPING_OPS} == 1) 
+  {
+    ALT_IDiv_S (format(A_AA_AAA) resv (RL_FAlu) latency(Lat5) flags(SILENT));
+    ALT_FAlu_S (format(A_AA_AAA) resv (RL_FAlu) latency(Lat5) flags(SILENT));
+    ALT_FMul_S (format(A_AA_AAA) resv (RL_FAlu) latency(Lat5) flags(SILENT));
+    ALT_FDiv_S (format(A_AA_AAA) resv (RL_FAlu) latency(Lat15) flags(SILENT));
+    ALT_Load_S (format(A_AA_AAA) resv (RL_Load) latency(Lat2) flags(SILENT));
+  }
+}
+
+/* This section entries groups together all the scheduling alternatives
+ * for each operation type.  In this simplified machine description, it
+ * is used only to add silent (non-trapping) versions of operations.
+ */
+SECTION Operation
+{
+  OP_IAlu       (alt(ALT_IAlu));    
+  OP_AAlu       (alt(ALT_AAlu));    
+  OP_IMul       (alt(ALT_IMul));     
+  OP_IDiv       (alt(ALT_IDiv));     
+  OP_INOP       (alt(ALT_INOP));     
+  OP_FAlu       (alt(ALT_FAlu));     
+  OP_FMul       (alt(ALT_FAlu));    
+  OP_FDiv       (alt(ALT_FDiv));     
+  OP_Load       (alt(ALT_Load));    
+  OP_Store      (alt(ALT_Store));   
+  OP_Branch     (alt(ALT_Branch));   
+  OP_JSR        (alt(ALT_JSR));     
+
+  /* Add silent versions to above (excepting) alternative lists,
+   *  if non-trapping operations are specified as being supported.
+   */
+  $if(${NON_TRAPPING_OPS} == 1) 
+  {
+    OP_IDiv     (alt||(ALT_IDiv_S));     
+    OP_FMul     (alt||(ALT_FMul_S));    
+    OP_FAlu     (alt||(ALT_FAlu_S));     
+    OP_FDiv     (alt||(ALT_FDiv_S));     
+    OP_Load     (alt||(ALT_Load_S));    
+  }
+}
+
+
+/* This section maps Lcode operations to scheduling alternatives (thru
+ * Operation entries).  It also describes to the scheduler and register
+ * allocator some properties of the operation (which they use instead
+ * of Lcode library calls).  It is very important to get these flags correct,
+ * otherwise the operation will be treated incorrectly and illegal
+ * schedules might result (i.e., must mark loads, stores, branches, etc.
+ * properly).
+ */
+SECTION IMPACT_Operation
+{
+  /* Compiler directives, the IGNORE flag tells the scheduler to ignore
+   * them (not schedule them, draw dependences to them, etc.) and put them 
+   * at the top of the cb after scheduling.  Just use OP_INOP since 
+   * something is needed.)
+   */
+  $for (OPC in Lop_DEFINE Lop_ALLOC Lop_PROLOGUE Lop_SIM_DIR Lop_BOUNDARY)
+  {
+      ${OPC}      (op(OP_INOP) flags (IGNORE));
+  }
+
+  /* EPILOGUE is a special compiler directive that must go just before
+   * the RTS (i.e, cannot move to top), so mark as SYNC operation
+   * (nothing will be able to move past it).
+   */
+  Lop_EPILOGUE  (op(OP_INOP) flags(SYNC));
+
+  /* Don't expect any no-ops, however better define */
+  Lop_NO_OP     (op(OP_INOP));
+
+  /* General check */
+  Lop_CHECK     (op(OP_INOP) flags (CHK));
+
+  /* Jump subroutine opcodes, must be marked with JSR flag! */
+  $for (OPC in Lop_JSR Lop_JSR_FS)
+  {
+      ${OPC}      (op(OP_JSR) flags (JSR));
+  }
+
+  /* Return to subroutines opcodes, must be marked with RTS flag! */
+  $for (OPC in Lop_RTS Lop_RTS_FS)
+  {
+      ${OPC}      (op(OP_JSR) flags (RTS));
+  }
+
+  /* Unconditinal jump opcodes, must be marked with JMP flag! */
+  $for (OPC in Lop_JUMP Lop_JUMP_FS Lop_JUMP_RG Lop_JUMP_RG_FS)
+  {
+      ${OPC}      (op(OP_Branch) flags (JMP));
+  }
+
+  /* Conditional jump opcodes, must be marked with CBR flag!
+   * Assume branch unit can compare any type of operand.
+   */
+  $for (OPC in Lop_BR Lop_BR_F)
+  {
+      ${OPC}      (op(OP_Branch) flags (CBR));
+  }
+
+  /* Integer Ialu operations, no flags needed */
+  $for (OPC in Lop_MOV Lop_ABS Lop_OR Lop_AND 
+               Lop_XOR Lop_NOR Lop_NAND Lop_NXOR      
+               Lop_OR_NOT Lop_AND_NOT Lop_OR_COMPL Lop_AND_COMPL 
+               Lop_ADD Lop_ADD_U Lop_SUB Lop_SUB_U Lop_RCMP
+	       Lop_EXTRACT_C Lop_EXTRACT_C2 Lop_EXTRACT Lop_EXTRACT_U Lop_DEPOSIT)
+  {
+      ${OPC}      (op(OP_AAlu));
+  }
+
+  $for (OPC in Lop_LSL Lop_LSR Lop_ASR)
+  {
+      ${OPC}      (op(OP_IAlu));
+  }
+
+  /* Integer multiple operations, no flags needed.
+   * Simplified, treat multiply_add ops, etc same as multiply.
+   */
+  $for (OPC in Lop_MUL Lop_MUL_U Lop_MUL_ADD Lop_MUL_ADD_U
+               Lop_MUL_SUB Lop_MUL_SUB_U Lop_MUL_SUB_REV Lop_MUL_SUB_REV_U)
+  {
+      ${OPC}      (op(OP_IMul));
+  }
+
+  /* Integer divide operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_DIV Lop_DIV_U Lop_REM Lop_REM_U)
+  {
+      ${OPC}      (op(OP_IDiv) flags (EXCEPT));
+  }
+
+  /* Floating-point moves, cannot except */
+  Lop_MOV_F     (op(OP_FAlu));
+  Lop_MOV_F2    (op(OP_FAlu));
+
+  /* Floating-point Ialu operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_ABS_F Lop_ABS_F2 Lop_ADD_F Lop_ADD_F2
+               Lop_SUB_F Lop_SUB_F2 Lop_RCMP_F)
+  {
+      ${OPC}      (op(OP_FAlu) flags (EXCEPT));
+  }
+
+  /* Floating-point multiple operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   * Simplified, treat multiply_add ops, etc same as multiply.
+   */
+  $for (OPC in Lop_MUL_F Lop_MUL_F2 Lop_MUL_ADD_F Lop_MUL_ADD_F2
+               Lop_MUL_SUB_F Lop_MUL_SUB_REV_F 
+               Lop_MUL_SUB_F2 Lop_MUL_SUB_REV_F2)
+  {
+      ${OPC}      (op(OP_FMul) flags (EXCEPT));
+  }
+
+  /* Floating-point divide operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   * Simplified, treat sqrt ops, etc same as divide.
+   */
+  $for (OPC in Lop_DIV_F Lop_DIV_F2 Lop_SQRT_F Lop_SQRT_F2)
+  {
+      ${OPC}      (op(OP_FDiv) flags (EXCEPT));
+  }
+
+  /* Loop over the possible data types for memory operations */
+  $for (TYPE in C C2 I F F2)
+  {
+    /* Load memory opcodes, must be marked with EXCEPT LOAD flag! 
+     * Will not speculate above branch unless one of the scheduling
+     * alternatives is a SILENT version.
+     * Pre and post increment loads (LD_PRE, LD_POST) are not currently 
+     * supported (as of IMPACT release 2.32).
+     */
+     Lop_LD_${TYPE} (op(OP_Load) flags (EXCEPT LOAD));
+
+
+    /* Store memory opcodes, must be marked with EXCEPT STORE flag! 
+     * Pre and post increment stores (ST_PRE, ST_POST) are not currently 
+     * supported (as of IMPACT release 2.32).
+     */
+     Lop_ST_${TYPE} (op(OP_Store) flags (EXCEPT STORE));
+  }
+
+  /* Unsigned character/short loads (there are no unsigned stores) */
+  Lop_LD_UC       (op(OP_Load) flags (EXCEPT LOAD));
+  Lop_LD_UC2      (op(OP_Load) flags (EXCEPT LOAD));
+
+  /* Predicate load/store operations */
+  Lop_PRED_LD     (op(OP_Load) flags(EXCEPT LOAD));
+  Lop_PRED_ST     (op(OP_Store) flags(EXCEPT STORE));
+
+  /* Load/store block of 32 predicate registers (used by register allocator) */
+  Lop_PRED_LD_BLK (op(OP_Load) flags(EXCEPT LOAD));
+  Lop_PRED_ST_BLK (op(OP_Store) flags(EXCEPT STORE));
+
+  /* PRED_CLEAR and PRED_SET clears/sets a single predicate, primarily for 
+   * the convenence of the compiler writer. They need to be folded into
+   * later predicate definitions (via optimizations) and the rest converted 
+   * into operations that set/clear multiple predicates (perhaps up to 32) 
+   * in a single operation.  Since these pred clear/set optimizations are
+   * not currently supported (as of IMPACT release 2.32), make an aggressive 
+   * assumption that they are free and ignore their cost by treating them 
+   * as compiler directives.  (The alternative, to treat them as regular 
+   * operations is way too conservative, since many of them can be folded 
+   * in with later predicate definitions (thus eliminated) and the rest
+   * can be converted into at least predicate definitions (which allow
+   * setting two predicates per operation).
+   */
+  Lop_PRED_CLEAR(op(OP_IAlu) flags(IGNORE));
+  Lop_PRED_SET  (op(OP_IAlu) flags(IGNORE));
+
+  /* Predicate definition opcodes using integer comparisons.
+   * No flags needed. 
+   */
+  $for (OPC in Lop_CMP)
+  {
+      ${OPC}      (op(OP_IAlu));
+  }
+
+  /* Predicate definition opcodes using floating-point comparisons.
+   * EXCEPT flag must be specified. Will not speculate above branch
+   * unless one of the scheduling alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_CMP_F)
+  {
+      ${OPC}      (op(OP_FAlu) flags (EXCEPT));
+  }
+  $for (OPC in Lop_F2_I Lop_I_F2 Lop_F_I Lop_I_F Lop_F2_F Lop_F_F2)
+  {
+      ${OPC}      (op(OP_FAlu) flags (EXCEPT));
+  }
+}
+
+
+
diff -urN openimpact-1.0rc4/mdes/Limpact/IMPACT_RES_BASE.hmdes openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_RES_BASE.hmdes
--- openimpact-1.0rc4/mdes/Limpact/IMPACT_RES_BASE.hmdes	1969-12-31 18:00:00.000000000 -0600
+++ openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_RES_BASE.hmdes	2004-09-17 14:41:03.000000000 -0500
@@ -0,0 +1,556 @@
+Version1
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%%
+%%		      Illinois Open Source License
+%%                     University of Illinois/NCSA
+%%                         Open Source License
+%%
+%% Copyright (c) 2004, The University of Illinois at Urbana-Champaign.
+%% All rights reserved.
+%%
+%% Developed by:             
+%%
+%%		IMPACT Research Group
+%%
+%%		University of Illinois at Urbana-Champaign
+%%
+%%              http://www.crhc.uiuc.edu/IMPACT
+%%              http://www.gelato.org
+%%
+%% Permission is hereby granted, free of charge, to any person
+%% obtaining a copy of this software and associated documentation
+%% files (the "Software"), to deal with the Software without
+%% restriction, including without limitation the rights to use, copy,
+%% modify, merge, publish, distribute, sublicense, and/or sell copies
+%% of the Software, and to permit persons to whom the Software is
+%% furnished to do so, subject to the following conditions:
+%%
+%% Redistributions of source code must retain the above copyright
+%% notice, this list of conditions and the following disclaimers.
+%%
+%% Redistributions in binary form must reproduce the above copyright
+%% notice, this list of conditions and the following disclaimers in
+%% the documentation and/or other materials provided with the
+%% distribution.
+%%
+%% Neither the names of the IMPACT Research Group, the University of
+%% Illinois, nor the names of its contributors may be used to endorse
+%% or promote products derived from this Software without specific
+%% prior written permission.  THE SOFTWARE IS PROVIDED "AS IS",
+%% WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
+%% LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+%% PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+%% CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
+%% OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+%% OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+%% OR THE USE OR OTHER DEALINGS WITH THE SOFTWARE.
+%%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% IMPACT v1.0 Architecture High-Level Machine Description
+% Issue 1, general percolation
+% Author: Scott A. Mahlke
+% Date:   6-93
+
+$define ISSUE	1
+$define BRANCH	1
+
+(Define declaration
+    C_header_file	"$IMPACT_ROOT$/include/Lcode/l_opc.h"
+    C_header_file	"$IMPACT_ROOT$/include/Lcode/l_flags.h"
+    C_header_file	"$IMPACT_ROOT$/include/Lcode/limpact_phase1.h"
+    C_header_file	"$IMPACT_ROOT$/include/machine/m_spec.h"
+    C_header_file	"$IMPACT_ROOT$/include/machine/m_impact.h"
+    predicates		1
+    dest_operands	2
+    dest_syncs		4	# Used to construct control/sync dependences
+    source_operands	4
+    src_syncs		4	# Used to construct control/sync dependences
+    processor_model     superscalar
+end)
+
+#
+# name ((capacity "static" "rotating") (width "size in bits"))
+#
+
+(Register_Files declaration
+    p       ((capacity 32 0) (width 32))
+    i	    ((capacity 64 0) (width 32))
+    f	    ((capacity 64 0) (width 32))
+    f2	    ((capacity 32 0) (width 64))
+    
+    # generic literal field  bit field for short loads/stores
+    Lit    ((capacity 0 0) (width 32))
+    
+    Label   ((capacity 0 0) (width 32))
+
+    NULL    ((capacity 0 0) (width 0))
+    
+end)
+
+#
+# name (reg_file1 ...)
+#
+
+(IO_Sets declaration
+    REG (p i f f2)
+    CON (Lit Label)
+    SOME (REG Lit Label)
+    ANY (REG Lit Label NULL)
+    RANY (REG NULL)
+    
+end)
+
+#
+# name (<predicate0 ...>[dest0 ...][src0 ...])
+#
+
+(IO_Items declaration
+    # Standard 3 operand instruction format
+    IOI_Std3 		(<RANY>[REG - ][SOME SOME - - ])
+    
+    # Standard 5 operand instruction format
+    IOI_Std5		(<RANY>[REG RANY][SOME SOME SOME -])
+
+    # Predicate clear
+    IOI_predclr		([REG -][- - - -])
+
+    # Predicate copy
+    IOI_predcopy	(<RANY>[REG -][- - - -])
+
+    # Predicate comparison
+    IOI_predcmp        (<RANY>[REG RANY][SOME SOME - - ])
+
+    # Operand format for "move"
+    IOI_mov 		(<RANY>[REG - ][SOME - - - ])
+    IOI_cmov            (<->   [REG - ][SOME SOME - -])
+    IOI_select          (<->   [REG - ][SOME SOME SOME -])
+
+    # Operand format for unconditional branch
+    # SAM 8/94 - 3 types of ubr, generic (ubr), predicated (pubr), 
+    #            non-predicated (npubr).  This is so can treat predicated
+    #            jumps just like conditional branches, but still handle other
+    #            unconditional brs like jrg and jsr separately
+    IOI_rts		(<RANY>[ - - ][ - - - -])
+    IOI_ubr             (<RANY>[ - - ][SOME ANY - - ])
+    IOI_npubr           (      [ - - ][SOME ANY - - ])
+    IOI_pubr            (<REG> [ - - ][SOME ANY - - ])
+   
+    # Operand format for conditional branch
+    IOI_cbr		(<RANY>[ - - ][SOME SOME CON - ])
+   
+    # Operand format for stores
+	# basic store
+    IOI_store1		(<RANY>[ - - ][SOME SOME SOME - ])
+    	# pre/post inc store
+    IOI_store2		(<RANY>[REG - ][SOME SOME SOME SOME ])
+
+    # Operand format for loads
+	# basic load
+    IOI_load1		(<RANY>[REG - ][SOME SOME - - ])
+    	# pre/post inc load
+    IOI_load2		(<RANY>[REG REG][SOME SOME SOME - ])
+
+    IOI_Nil (<RANY>[][])
+    IOI_Ch (<RANY>[][ANY ANY ANY])
+    IOI_Ignore  (<ANY>[ANY ANY][ANY ANY ANY ANY])
+end)
+
+# Enumerate resources
+
+(Resources declaration
+    slot[0..$ISSUE$]
+    ialu[0..$ISSUE$]
+    imul[0..$ISSUE$]
+    idiv[0..$ISSUE$]
+    fpalu[0..$ISSUE$]
+    fpmul[0..$ISSUE$]
+    fpdiv[0..$ISSUE$]
+    mem[0..$ISSUE$]
+    branch[0..$BRANCH$]
+end)
+
+(ResTables declaration
+    RL_INOP    ( # 1 cycle NOP
+    			(slot 0)
+	       )
+    RL_IAlu    ( # 1 cycle IAlu
+    			(slot 0)
+			(ialu 0)
+	       )
+    RL_IMul    ( # fully pipelined IMul
+			(slot 0)
+			(imul 0)
+	       )
+    RL_IDiv    ( # fully pipelined IDiv
+			(slot 0)
+			(idiv 0)
+	       )
+    RL_FPAlu   ( # fully pipelined single/double precision fp alu op 
+    			(slot 0)
+			(fpalu 0)
+	       )
+    RL_FPMul   ( # fully pipelined single/double precision fp multiply
+    			(slot 0)
+    			(fpmul 0)
+	       )
+    RL_FPDiv   ( # fully pipelined single/double precision fp divide
+    			(slot 0)
+    			(fpdiv 0)
+	       )
+    RL_Load    ( # fully pipelined load
+		 	(slot 0)
+			(mem 0)
+    	       )
+    RL_Store   ( # fully pipelined store
+    			(slot 0)
+			(mem  0)
+    	       )
+    RL_Branch  ( # fully pipelined branch
+			(slot 0)
+			(branch 0)
+               )
+end)
+
+
+# 
+# name (exception_latency (pred) (dest0 ...) (src0 ...) (sync_dest ...) (sync_src ...)
+#
+#       Sync arcs description   1: memory
+#                               2: control
+#                               3: synchronization
+#                               4: vliw (special use, set to 0)
+
+(Latencies declaration
+    Lat1    ( 1 (0) (1 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))
+    Lat1ma  ( 1 (0) (0 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# st
+    Lat1mb  ( 1 (0) (1 0) (0 0 0 0) (1 0 0 0) (0 0 0 0))	# post/pre inc st
+    Lat1ba  ( 1 (0) (1 0) (0 0 0 0) (0 1 0 0) (0 0 0 0))	# uncond branches
+    Lat1bb  ( 1 (0) (1 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# int cond branches
+    Lat1p   ( 1 (0) (1 1) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# int pred compares
+    Lat2ma  ( 2 (0) (2 0) (0 0 0 0) (1 0 0 0) (0 0 0 0))	# ld
+    Lat2mb  ( 2 (0) (2 1) (0 0 0 0) (1 0 0 0) (0 0 0 0))	# post/pre inc ld
+
+# Lat3's changed to 2 cycles to match HPPA - SAM 9-94
+    Lat3    ( 2 (0) (2 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))
+    Lat3a   ( 2 (0) (2 2) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# mul_add, mul_sub
+    Lat3bb  ( 2 (0) (2 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# flt/dbl cond branches
+    Lat3p   ( 2 (0) (2 2) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# flt/dbl pred compares
+    Lat10   ( 10 (0) (10 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))
+end)
+    
+# name ((io_list, resource_list, latency) ...())
+(Operation_class declaration
+	CL_Ignore
+		(
+			(IOI_Ignore RL_INOP Lat1)
+		)
+end)
+
+# lcode_name <op_flags> (assembly_name <alt_flags> (operation_class))
+#
+# The following op_flags are supported:
+#       op_flags must be the same across common lcode_names
+#
+#       IGNORE - scheduler ignores this op
+#       CBR - conditional branch op
+#       JMP - unconditional branch op
+#       JSR - subroutine call
+#       RTS - subroutine return
+#       SYNC - synchronization op
+#       LOAD - load op
+#       STORE - store op
+#       EXCEPT - op may cause an exception
+#
+# The following alt_flags are supported:
+#       alternative flags may be different across common lcode_names
+#
+#       SILENT - speculative version
+
+(Operations declaration 
+
+# Lcode opcodes that are ignored by scheduler
+	Lop_DEFINE	<IGNORE>        (Lop_DEFINE	           CL_Ignore)
+	Lop_ALLOC	<IGNORE>        (Lop_ALLOC	           CL_Ignore)
+	Lop_EPILOGUE	<SYNC>          (Lop_EPILOGUE	           CL_Ignore)
+	Lop_PROLOGUE	<IGNORE>        (Lop_PROLOGUE	           CL_Ignore)
+	Lop_SIM_DIR	<IGNORE>        (Lop_SIM_DIR	           CL_Ignore)
+	Lop_BOUNDARY    <IGNORE>        (Lop_BOUNDARY              CL_Ignore)
+	
+# The remaining opcodes are supported by the scheduler
+	Lop_NO_OP   		        (Lop_NO_OP               ((IOI_Nil  RL_INOP  Lat1)) )
+        Lop_CHECK       <CHK>   	(Lop_CHECK   		 ((IOI_Ch   RL_INOP  Lat1)) )
+        Lop_CONFIRM     <CHK>   	(Lop_CONFIRM 		 ((IOI_Ch   RL_INOP  Lat1)) )
+ 
+ 	Lop_JSR		<JSR> 	        (Lop_JSR                 ((IOI_ubr  RL_Branch  Lat1ba)) )
+ 	Lop_JSR_FS	<JSR> 	        (Lop_JSR_FS              ((IOI_ubr  RL_Branch  Lat1ba)) )
+
+    	Lop_RTS		<RTS>	        (Lop_RTS                 ((IOI_rts  RL_Branch  Lat1ba)) )
+    	Lop_RTS_FS	<RTS>	        (Lop_RTS_FS              ((IOI_rts  RL_Branch  Lat1ba)) )
+
+    	Lop_JUMP	<JMP>           (Lop_JUMP                ((IOI_npubr  RL_Branch  Lat1ba)) )
+    	Lop_JUMP	<JMP>           (Lop_JUMP                ((IOI_pubr  RL_Branch  Lat1bb)) )
+	Lop_JUMP_FS	<JMP> 	        (Lop_JUMP_FS             ((IOI_npubr  RL_Branch  Lat1ba)) )
+	Lop_JUMP_FS	<JMP> 	        (Lop_JUMP_FS             ((IOI_pubr  RL_Branch  Lat1bb)) )
+
+	Lop_JUMP_RG	<JMP>	        (Lop_JUMP_RG             ((IOI_ubr  RL_Branch  Lat1ba)) )
+      	Lop_JUMP_RG_FS	<JMP>	        (Lop_JUMP_RG_FS          ((IOI_ubr  RL_Branch  Lat1ba)) )
+
+# Conditional branch instructions
+
+	Lop_BEQ         <CBR>           (Lop_BEQ                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BEQ_FS      <CBR>           (Lop_BEQ_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BNE         <CBR>           (Lop_BNE                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BNE_FS      <CBR>           (Lop_BNE_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGT         <CBR>           (Lop_BGT                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGT_FS      <CBR>           (Lop_BGT_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE         <CBR>           (Lop_BGE                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE_FS      <CBR>           (Lop_BGE_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT         <CBR>           (Lop_BLT                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT_FS      <CBR>           (Lop_BLT_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE         <CBR>           (Lop_BLE                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE_FS      <CBR>           (Lop_BLE_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+
+	Lop_BGT_U       <CBR>           (Lop_BGT_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGT_U_FS    <CBR>           (Lop_BGT_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE_U       <CBR>           (Lop_BGE_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE_U_FS    <CBR>           (Lop_BGE_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT_U       <CBR>           (Lop_BLT_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT_U_FS    <CBR>           (Lop_BLT_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE_U       <CBR>           (Lop_BLE_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE_U_FS    <CBR>           (Lop_BLE_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+
+	Lop_BEQ_F       <CBR EXCEPT>    (Lop_BEQ_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BEQ_F_FS    <CBR EXCEPT>    (Lop_BEQ_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F       <CBR EXCEPT>    (Lop_BNE_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F_FS    <CBR EXCEPT>    (Lop_BNE_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F       <CBR EXCEPT>    (Lop_BGT_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F_FS    <CBR EXCEPT>    (Lop_BGT_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F       <CBR EXCEPT>    (Lop_BGE_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F_FS    <CBR EXCEPT>    (Lop_BGE_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F       <CBR EXCEPT>    (Lop_BLT_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F_FS    <CBR EXCEPT>    (Lop_BLT_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F       <CBR EXCEPT>    (Lop_BLE_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F_FS    <CBR EXCEPT>    (Lop_BLE_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+
+	Lop_BEQ_F2      <CBR EXCEPT>    (Lop_BEQ_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BEQ_F2_FS   <CBR EXCEPT>    (Lop_BEQ_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F2      <CBR EXCEPT>    (Lop_BNE_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F2_FS   <CBR EXCEPT>    (Lop_BNE_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F2      <CBR EXCEPT>    (Lop_BGT_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F2_FS   <CBR EXCEPT>    (Lop_BGT_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F2      <CBR EXCEPT>    (Lop_BGE_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F2_FS   <CBR EXCEPT>    (Lop_BGE_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F2      <CBR EXCEPT>    (Lop_BLT_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F2_FS   <CBR EXCEPT>    (Lop_BLT_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F2      <CBR EXCEPT>    (Lop_BLE_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F2_FS   <CBR EXCEPT>    (Lop_BLE_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+
+# Integer ALU instructions
+
+	Lop_MOV	                        (Lop_MOV                 ((IOI_mov RL_IAlu  Lat1)) )
+	Lop_ABS	                        (Lop_ABS                 ((IOI_mov RL_IAlu  Lat1)) )
+	
+    	Lop_OR	                        (Lop_OR                  ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_AND	                        (Lop_AND                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_XOR	                        (Lop_XOR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_NOR	                        (Lop_NOR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_NAND                        (Lop_NAND                ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_NXOR                        (Lop_NXOR                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_OR_NOT                      (Lop_OR_NOT              ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_AND_NOT                     (Lop_AND_NOT             ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_OR_COMPL                    (Lop_OR_COMPL            ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_AND_COMPL                   (Lop_AND_COMPL           ((IOI_Std3  RL_IAlu  Lat1)) )
+
+	Lop_LSL	                        (Lop_LSL                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_LSR	                        (Lop_LSR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_ASR	                        (Lop_ASR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+
+	Lop_ADD	                        (Lop_ADD                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_ADD_U                       (Lop_ADD_U               ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_SUB	                        (Lop_SUB                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_SUB_U                       (Lop_SUB_U               ((IOI_Std3  RL_IAlu  Lat1)) )
+	
+				    
+# Integer comparison instructions
+
+    	Lop_EQ	                        (Lop_EQ                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_NE	                        (Lop_NE                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GT	                        (Lop_GT                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GT_U                        (Lop_GT_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GE	                        (Lop_GE                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GE_U                        (Lop_GE_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LT	                        (Lop_LT                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LT_U                        (Lop_LT_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LE	                        (Lop_LE                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LE_U                        (Lop_LE_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+
+# Misc integer instructions
+
+	Lop_MUL	                     (Lop_MUL                 ((IOI_Std3  RL_IMul  Lat3)) )
+	Lop_MUL_U                    (Lop_MUL_U               ((IOI_Std3  RL_IMul  Lat3)) )
+	Lop_DIV	        <EXCEPT>        (Lop_DIV                 ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_DIV_U       <EXCEPT>        (Lop_DIV_U               ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_REM	        <EXCEPT>        (Lop_REM                 ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_REM_U       <EXCEPT>        (Lop_REM_U               ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_MUL_ADD                     (Lop_MUL_ADD             ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_ADD_U                   (Lop_MUL_ADD_U           ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB                     (Lop_MUL_SUB             ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB_U                   (Lop_MUL_SUB_U           ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB_REV                 (Lop_MUL_SUB_REV         ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB_REV_U               (Lop_MUL_SUB_REV_U       ((IOI_Std5  RL_IMul  Lat3)) )
+	
+# Floating point ALU instructions
+
+	Lop_MOV_F    		        (Lop_MOV_F               ((IOI_mov   RL_FPAlu  Lat1)) )
+	Lop_MOV_F2    		        (Lop_MOV_F2              ((IOI_mov   RL_FPAlu  Lat1)) )
+        Lop_ABS_F       <EXCEPT>        (Lop_ABS_F               ((IOI_mov   RL_FPAlu  Lat1)) )
+        Lop_ABS_F2      <EXCEPT>        (Lop_ABS_F2              ((IOI_mov   RL_FPAlu  Lat1)) )
+
+
+      	Lop_ADD_F       <EXCEPT>   	(Lop_ADD_F               ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_ADD_F2      <EXCEPT>   	(Lop_ADD_F2              ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_SUB_F       <EXCEPT>   	(Lop_SUB_F               ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_SUB_F2      <EXCEPT>   	(Lop_SUB_F2              ((IOI_Std3  RL_FPAlu  Lat3)) )
+
+# Floating point comparison instructions
+
+	Lop_EQ_F        <EXCEPT>  	(Lop_EQ_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_EQ_F2       <EXCEPT>  	(Lop_EQ_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_NE_F        <EXCEPT>  	(Lop_NE_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_NE_F2       <EXCEPT>  	(Lop_NE_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GT_F        <EXCEPT>  	(Lop_GT_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GT_F2       <EXCEPT>  	(Lop_GT_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GE_F        <EXCEPT>  	(Lop_GE_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GE_F2       <EXCEPT>  	(Lop_GE_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LT_F        <EXCEPT>  	(Lop_LT_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LT_F2       <EXCEPT>  	(Lop_LT_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LE_F        <EXCEPT>  	(Lop_LE_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LE_F2       <EXCEPT>  	(Lop_LE_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+
+# Float point conversion instructions
+
+    	Lop_I_F	        <EXCEPT>	(Lop_I_F                 ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F_I	        <EXCEPT>	(Lop_F_I                 ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_I_F2        <EXCEPT>	(Lop_I_F2                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F2_I        <EXCEPT>	(Lop_F2_I                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F_F2        <EXCEPT>	(Lop_F_F2                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F2_F        <EXCEPT>	(Lop_F2_F                ((IOI_mov   RL_FPAlu  Lat3)) )
+
+# Misc floating point instructions 
+
+	Lop_MUL_F       <EXCEPT>	(Lop_MUL_F          	 ((IOI_Std3  RL_FPMul  Lat3)) )
+	Lop_MUL_F2      <EXCEPT>	(Lop_MUL_F2     	 ((IOI_Std3  RL_FPMul  Lat3)) )
+	Lop_DIV_F       <EXCEPT>	(Lop_DIV_F	         ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_DIV_F2      <EXCEPT>	(Lop_DIV_F2	         ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_MUL_ADD_F   <EXCEPT>        (Lop_MUL_ADD_F	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_ADD_F2  <EXCEPT>        (Lop_MUL_ADD_F2	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_F   <EXCEPT>        (Lop_MUL_SUB_F	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_REV_F  <EXCEPT>     (Lop_MUL_SUB_REV_F	 ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_F2  <EXCEPT>        (Lop_MUL_SUB_F2	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_REV_F2 <EXCEPT>     (Lop_MUL_SUB_REV_F2	 ((IOI_Std5  RL_FPMul  Lat3)) )
+        Lop_SQRT_F       <EXCEPT>       (Lop_SQRT_F              ((IOI_Std3  RL_FPDiv  Lat10)) )
+        Lop_SQRT_F2      <EXCEPT>       (Lop_SQRT_F2             ((IOI_Std3  RL_FPDiv  Lat10)) )
+
+	
+# Load instructions
+
+	Lop_LD_UC	<LOAD EXCEPT>	(Lop_LD_UC               ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_UC	<LOAD EXCEPT>	(Lop_LD_PRE_UC           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_UC	<LOAD EXCEPT>	(Lop_LD_POST_UC          ((IOI_load2 RL_Load Lat2mb)) )
+
+	Lop_LD_C	<LOAD EXCEPT>	(Lop_LD_C                ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_C	<LOAD EXCEPT>	(Lop_LD_PRE_C            ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_C	<LOAD EXCEPT>	(Lop_LD_POST_C           ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_UC2	<LOAD EXCEPT>	(Lop_LD_UC2              ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_UC2	<LOAD EXCEPT>	(Lop_LD_PRE_UC2          ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_UC2	<LOAD EXCEPT>	(Lop_LD_POST_UC2         ((IOI_load2 RL_Load Lat2mb)) )
+
+	Lop_LD_C2	<LOAD EXCEPT>	(Lop_LD_C2               ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_C2	<LOAD EXCEPT>	(Lop_LD_PRE_C2           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_C2	<LOAD EXCEPT>	(Lop_LD_POST_C2          ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_I	<LOAD EXCEPT>	(Lop_LD_I                ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_I	<LOAD EXCEPT>	(Lop_LD_PRE_I            ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_I	<LOAD EXCEPT>	(Lop_LD_POST_I           ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_F	<LOAD EXCEPT>	(Lop_LD_F                ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_F	<LOAD EXCEPT>	(Lop_LD_PRE_F            ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_F	<LOAD EXCEPT>	(Lop_LD_POST_F           ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_F2	<LOAD EXCEPT>	(Lop_LD_F2               ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_F2	<LOAD EXCEPT>	(Lop_LD_PRE_F2           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_F2	<LOAD EXCEPT>	(Lop_LD_POST_F2          ((IOI_load2 RL_Load Lat2mb)) )
+	
+# Store instructions
+
+	Lop_ST_C	<STORE EXCEPT>	(Lop_ST_C                ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_C	<STORE EXCEPT>	(Lop_ST_PRE_C            ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_C	<STORE EXCEPT>	(Lop_ST_POST_C           ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_C2	<STORE EXCEPT>	(Lop_ST_C2               ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_C2	<STORE EXCEPT>	(Lop_ST_PRE_C2           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_C2	<STORE EXCEPT>	(Lop_ST_POST_C2          ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_I	<STORE EXCEPT>	(Lop_ST_I                ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_I	<STORE EXCEPT>	(Lop_ST_PRE_I            ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_I	<STORE EXCEPT>	(Lop_ST_POST_I           ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_F	<STORE EXCEPT>	(Lop_ST_F                ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_F	<STORE EXCEPT>	(Lop_ST_PRE_F            ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_F	<STORE EXCEPT>	(Lop_ST_POST_F           ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_F2	<STORE EXCEPT>	(Lop_ST_F2               ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_F2	<STORE EXCEPT>	(Lop_ST_PRE_F2           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_F2	<STORE EXCEPT>	(Lop_ST_POST_F2          ((IOI_store2 RL_Store Lat1mb)) )
+
+# Predicate setting instructions
+
+	Lop_PRED_CLEAR                  (Lop_PRED_CLEAR		 ((IOI_predclr RL_IAlu Lat1)) )
+	Lop_PRED_SET                    (Lop_PRED_SET		 ((IOI_predclr RL_IAlu Lat1)) )
+	Lop_PRED_COPY                   (Lop_PRED_COPY		 ((IOI_predcopy RL_IAlu Lat1)) )
+
+	Lop_PRED_LD	<LOAD EXCEPT>	(Lop_PRED_LD		 ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_PRED_LD_BLK	<LOAD EXCEPT>	(Lop_PRED_LD_BLK	 ((IOI_load1 RL_Load Lat2ma)) )
+
+	Lop_PRED_ST	<STORE EXCEPT>	(Lop_PRED_ST		 ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_PRED_ST_BLK	<STORE EXCEPT>	(Lop_PRED_ST_BLK	 ((IOI_store1 RL_Store Lat1ma)) )
+
+	Lop_PRED_EQ			(Lop_PRED_EQ		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_NE			(Lop_PRED_NE		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GT			(Lop_PRED_GT		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GT_U			(Lop_PRED_GT_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GE			(Lop_PRED_GE		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GE_U			(Lop_PRED_GE_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LT			(Lop_PRED_LT		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LT_U			(Lop_PRED_LT_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LE			(Lop_PRED_LE		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LE_U			(Lop_PRED_LE_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+
+	Lop_PRED_EQ_F2	<EXCEPT>	(Lop_PRED_EQ_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_NE_F2	<EXCEPT>	(Lop_PRED_NE_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GT_F2	<EXCEPT>	(Lop_PRED_GT_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GE_F2	<EXCEPT>	(Lop_PRED_GE_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LT_F2	<EXCEPT>	(Lop_PRED_LT_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LE_F2	<EXCEPT>	(Lop_PRED_LE_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+
+	Lop_PRED_EQ_F	<EXCEPT>	(Lop_PRED_EQ_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_NE_F	<EXCEPT>	(Lop_PRED_NE_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GT_F	<EXCEPT>	(Lop_PRED_GT_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GE_F	<EXCEPT>	(Lop_PRED_GE_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LT_F	<EXCEPT>	(Lop_PRED_LT_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LE_F	<EXCEPT>	(Lop_PRED_LE_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+
+        Lop_CMOV                        (Lop_CMOV                ((IOI_cmov RL_IAlu  Lat1)) )
+        Lop_CMOV_COM                    (Lop_CMOV_COM            ((IOI_cmov RL_IAlu  Lat1)) )
+        Lop_CMOV_F                      (Lop_CMOV_F              ((IOI_cmov RL_FPAlu Lat1)) )
+        Lop_CMOV_COM_F                  (Lop_CMOV_COM_F          ((IOI_cmov RL_FPAlu Lat1)) )
+        Lop_CMOV_F2                     (Lop_CMOV_F2             ((IOI_cmov RL_FPAlu Lat1)) )
+        Lop_CMOV_COM_F2                 (Lop_CMOV_COM_F2         ((IOI_cmov RL_FPAlu Lat1)) )
+
+        Lop_SELECT                      (Lop_SELECT              ((IOI_select RL_IAlu  Lat1)) )
+        Lop_SELECT_F                    (Lop_SELECT_F            ((IOI_select RL_FPAlu Lat1)) )
+        Lop_SELECT_F2                   (Lop_SELECT_F2           ((IOI_select RL_FPAlu Lat1)) )
+
+end)
diff -urN openimpact-1.0rc4/mdes/Limpact/IMPACT_RES_NEWPRED_BASE.hmdes openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_RES_NEWPRED_BASE.hmdes
--- openimpact-1.0rc4/mdes/Limpact/IMPACT_RES_NEWPRED_BASE.hmdes	1969-12-31 18:00:00.000000000 -0600
+++ openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_RES_NEWPRED_BASE.hmdes	2004-09-17 14:41:03.000000000 -0500
@@ -0,0 +1,563 @@
+Version1
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%%
+%%		      Illinois Open Source License
+%%                     University of Illinois/NCSA
+%%                         Open Source License
+%%
+%% Copyright (c) 2004, The University of Illinois at Urbana-Champaign.
+%% All rights reserved.
+%%
+%% Developed by:             
+%%
+%%		IMPACT Research Group
+%%
+%%		University of Illinois at Urbana-Champaign
+%%
+%%              http://www.crhc.uiuc.edu/IMPACT
+%%              http://www.gelato.org
+%%
+%% Permission is hereby granted, free of charge, to any person
+%% obtaining a copy of this software and associated documentation
+%% files (the "Software"), to deal with the Software without
+%% restriction, including without limitation the rights to use, copy,
+%% modify, merge, publish, distribute, sublicense, and/or sell copies
+%% of the Software, and to permit persons to whom the Software is
+%% furnished to do so, subject to the following conditions:
+%%
+%% Redistributions of source code must retain the above copyright
+%% notice, this list of conditions and the following disclaimers.
+%%
+%% Redistributions in binary form must reproduce the above copyright
+%% notice, this list of conditions and the following disclaimers in
+%% the documentation and/or other materials provided with the
+%% distribution.
+%%
+%% Neither the names of the IMPACT Research Group, the University of
+%% Illinois, nor the names of its contributors may be used to endorse
+%% or promote products derived from this Software without specific
+%% prior written permission.  THE SOFTWARE IS PROVIDED "AS IS",
+%% WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
+%% LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+%% PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+%% CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
+%% OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+%% OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+%% OR THE USE OR OTHER DEALINGS WITH THE SOFTWARE.
+%%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% IMPACT v1.0 Architecture High-Level Machine Description
+% Issue 1, general percolation
+% Author: Scott A. Mahlke
+% Date:   6-93
+
+$define ISSUE	1
+$define BRANCH	1
+
+(Define declaration
+    C_header_file	"$IMPACT_ROOT$/include/Lcode/l_opc.h"
+    C_header_file	"$IMPACT_ROOT$/include/Lcode/l_flags.h"
+    C_header_file	"$IMPACT_ROOT$/include/Lcode/limpact_phase1.h"
+    C_header_file	"$IMPACT_ROOT$/include/machine/m_spec.h"
+    C_header_file	"$IMPACT_ROOT$/include/machine/m_impact.h"
+    predicates		1
+    dest_operands	16
+    dest_syncs		4	# Used to construct control/sync dependences
+    source_operands	16
+    src_syncs		4	# Used to construct control/sync dependences
+    processor_model     superscalar
+end)
+
+#
+# name ((capacity "static" "rotating") (width "size in bits"))
+#
+
+(Register_Files declaration
+    p       ((capacity 32 0) (width 32))
+    i	    ((capacity 64 0) (width 32))
+    f	    ((capacity 64 0) (width 32))
+    f2	    ((capacity 32 0) (width 64))
+    
+    # generic literal field  bit field for short loads/stores
+    Lit    ((capacity 0 0) (width 32))
+    
+    Label   ((capacity 0 0) (width 32))
+
+    NULL    ((capacity 0 0) (width 0))
+    
+end)
+
+#
+# name (reg_file1 ...)
+#
+
+(IO_Sets declaration
+    REG (p i f f2)
+    CON (Lit Label)
+    SOME (REG Lit Label)
+    ANY (REG Lit Label NULL)
+    RANY (REG NULL)
+    
+end)
+
+#
+# name (<predicate0 ...>[dest0 ...][src0 ...])
+#
+
+(IO_Items declaration
+    # Standard 3 operand instruction format
+    IOI_Std3 		(<RANY>[REG - ][SOME SOME - - ])
+    
+    # Standard 5 operand instruction format
+    IOI_Std5		(<RANY>[REG RANY][SOME SOME SOME -])
+
+    # Predicate clear
+    IOI_predclr		([REG -][- - - -])
+
+    # Predicate copy
+    IOI_predcopy	(<RANY>[REG -][- - - -])
+
+    # Predicate comparison
+
+    IOI_predcmp        (<RANY>[REG RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY][SOME SOME - - ])
+
+    IOI_pred_mask_combine    (<RANY>[REG - ][REG RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY RANY ])
+
+    # Operand format for "move"
+    IOI_mov 		(<RANY>[REG - ][SOME - - - ])
+    IOI_cmov            (<->   [REG - ][SOME SOME - -])
+    IOI_select          (<->   [REG - ][SOME SOME SOME -])
+
+    # Operand format for unconditional branch
+    # SAM 8/94 - 3 types of ubr, generic (ubr), predicated (pubr), 
+    #            non-predicated (npubr).  This is so can treat predicated
+    #            jumps just like conditional branches, but still handle other
+    #            unconditional brs like jrg and jsr separately
+    IOI_rts		(<RANY>[ - - ][ - - - -])
+    IOI_ubr             (<RANY>[ - - ][SOME ANY - - ])
+    IOI_npubr           (      [ - - ][SOME ANY - - ])
+    IOI_pubr            (<REG> [ - - ][SOME ANY - - ])
+   
+    # Operand format for conditional branch
+    IOI_cbr		(<RANY>[ - - ][SOME SOME CON - ])
+   
+    # Operand format for stores
+	# basic store
+    IOI_store1		(<RANY>[ - - ][SOME SOME SOME - ])
+    	# pre/post inc store
+    IOI_store2		(<RANY>[REG - ][SOME SOME SOME SOME ])
+
+    # Operand format for loads
+	# basic load
+    IOI_load1		(<RANY>[REG - ][SOME SOME - - ])
+    	# pre/post inc load
+    IOI_load2		(<RANY>[REG REG][SOME SOME SOME - ])
+
+    IOI_Nil (<RANY>[][])
+    IOI_Ch (<RANY>[][ANY ANY ANY])
+    IOI_Ignore  (<ANY>[ANY ANY][ANY ANY ANY ANY])
+end)
+
+# Enumerate resources
+
+(Resources declaration
+    slot[0..$ISSUE$]
+    ialu[0..$ISSUE$]
+    imul[0..$ISSUE$]
+    idiv[0..$ISSUE$]
+    fpalu[0..$ISSUE$]
+    fpmul[0..$ISSUE$]
+    fpdiv[0..$ISSUE$]
+    mem[0..$ISSUE$]
+    branch[0..$BRANCH$]
+end)
+
+(ResTables declaration
+    RL_INOP    ( # 1 cycle NOP
+    			(slot 0)
+	       )
+    RL_IAlu    ( # 1 cycle IAlu
+    			(slot 0)
+			(ialu 0)
+	       )
+    RL_IMul    ( # fully pipelined IMul
+			(slot 0)
+			(imul 0)
+	       )
+    RL_IDiv    ( # fully pipelined IDiv
+			(slot 0)
+			(idiv 0)
+	       )
+    RL_FPAlu   ( # fully pipelined single/double precision fp alu op 
+    			(slot 0)
+			(fpalu 0)
+	       )
+    RL_FPMul   ( # fully pipelined single/double precision fp multiply
+    			(slot 0)
+    			(fpmul 0)
+	       )
+    RL_FPDiv   ( # fully pipelined single/double precision fp divide
+    			(slot 0)
+    			(fpdiv 0)
+	       )
+    RL_Load    ( # fully pipelined load
+		 	(slot 0)
+			(mem 0)
+    	       )
+    RL_Store   ( # fully pipelined store
+    			(slot 0)
+			(mem  0)
+    	       )
+    RL_Branch  ( # fully pipelined branch
+			(slot 0)
+			(branch 0)
+               )
+end)
+
+
+# 
+# name (exception_latency (pred) (dest0 ...) (src0 ...) (sync_dest ...) (sync_src ...)
+#
+#       Sync arcs description   1: memory
+#                               2: control
+#                               3: synchronization
+#                               4: vliw (special use, set to 0)
+
+(Latencies declaration
+    Lat0pc  ( 0 (0) (0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 0) (0 0 0 0))
+    Lat1    ( 1 (0) (1 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))
+    Lat1ma  ( 1 (0) (0 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# st
+    Lat1mb  ( 1 (0) (1 0) (0 0 0 0) (1 0 0 0) (0 0 0 0))	# post/pre inc st
+    Lat1ba  ( 1 (0) (1 0) (0 0 0 0) (0 1 0 0) (0 0 0 0))	# uncond branches
+    Lat1bb  ( 1 (0) (1 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# int cond branches
+    Lat1p   ( 1 (0) (1 1) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# int pred compares
+    Lat2ma  ( 2 (0) (2 0) (0 0 0 0) (1 0 0 0) (0 0 0 0))	# ld
+    Lat2mb  ( 2 (0) (2 1) (0 0 0 0) (1 0 0 0) (0 0 0 0))	# post/pre inc ld
+
+# Lat3's changed to 2 cycles to match HPPA - SAM 9-94
+    Lat3    ( 2 (0) (2 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))
+    Lat3a   ( 2 (0) (2 2) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# mul_add, mul_sub
+    Lat3bb  ( 2 (0) (2 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# flt/dbl cond branches
+    Lat3p   ( 2 (0) (2 2) (0 0 0 0) (0 0 0 0) (0 0 0 0))	# flt/dbl pred compares
+    Lat10   ( 10 (0) (10 0) (0 0 0 0) (0 0 0 0) (0 0 0 0))
+end)
+    
+# name ((io_list, resource_list, latency) ...())
+(Operation_class declaration
+	CL_Ignore
+		(
+			(IOI_Ignore RL_INOP Lat1)
+		)
+end)
+
+# lcode_name <op_flags> (assembly_name <alt_flags> (operation_class))
+#
+# The following op_flags are supported:
+#       op_flags must be the same across common lcode_names
+#
+#       IGNORE - scheduler ignores this op
+#       CBR - conditional branch op
+#       JMP - unconditional branch op
+#       JSR - subroutine call
+#       RTS - subroutine return
+#       SYNC - synchronization op
+#       LOAD - load op
+#       STORE - store op
+#       EXCEPT - op may cause an exception
+#
+# The following alt_flags are supported:
+#       alternative flags may be different across common lcode_names
+#
+#       SILENT - speculative version
+
+(Operations declaration 
+
+# Lcode opcodes that are ignored by scheduler
+	Lop_DEFINE	<IGNORE>        (Lop_DEFINE	           CL_Ignore)
+	Lop_ALLOC	<IGNORE>        (Lop_ALLOC	           CL_Ignore)
+	Lop_EPILOGUE	<SYNC>          (Lop_EPILOGUE	           CL_Ignore)
+	Lop_PROLOGUE	<IGNORE>        (Lop_PROLOGUE	           CL_Ignore)
+	Lop_SIM_DIR	<IGNORE>        (Lop_SIM_DIR	           CL_Ignore)
+	Lop_BOUNDARY    <IGNORE>        (Lop_BOUNDARY              CL_Ignore)
+	
+# The remaining opcodes are supported by the scheduler
+	Lop_NO_OP   		        (Lop_NO_OP               ((IOI_Nil  RL_INOP  Lat1)) )
+        Lop_CHECK       <CHK>   	(Lop_CHECK   		 ((IOI_Ch   RL_INOP  Lat1)) )
+        Lop_CONFIRM     <CHK>   	(Lop_CONFIRM 		 ((IOI_Ch   RL_INOP  Lat1)) )
+ 
+ 	Lop_JSR		<JSR> 	        (Lop_JSR                 ((IOI_ubr  RL_Branch  Lat1ba)) )
+ 	Lop_JSR_FS	<JSR> 	        (Lop_JSR_FS              ((IOI_ubr  RL_Branch  Lat1ba)) )
+
+    	Lop_RTS		<RTS>	        (Lop_RTS                 ((IOI_rts  RL_Branch  Lat1ba)) )
+    	Lop_RTS_FS	<RTS>	        (Lop_RTS_FS              ((IOI_rts  RL_Branch  Lat1ba)) )
+
+    	Lop_JUMP	<JMP>           (Lop_JUMP                ((IOI_npubr  RL_Branch  Lat1ba)) )
+    	Lop_JUMP	<JMP>           (Lop_JUMP                ((IOI_pubr  RL_Branch  Lat1bb)) )
+	Lop_JUMP_FS	<JMP> 	        (Lop_JUMP_FS             ((IOI_npubr  RL_Branch  Lat1ba)) )
+	Lop_JUMP_FS	<JMP> 	        (Lop_JUMP_FS             ((IOI_pubr  RL_Branch  Lat1bb)) )
+
+	Lop_JUMP_RG	<JMP>	        (Lop_JUMP_RG             ((IOI_ubr  RL_Branch  Lat1ba)) )
+      	Lop_JUMP_RG_FS	<JMP>	        (Lop_JUMP_RG_FS          ((IOI_ubr  RL_Branch  Lat1ba)) )
+
+# Conditional branch instructions
+
+	Lop_BEQ         <CBR>           (Lop_BEQ                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BEQ_FS      <CBR>           (Lop_BEQ_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BNE         <CBR>           (Lop_BNE                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BNE_FS      <CBR>           (Lop_BNE_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGT         <CBR>           (Lop_BGT                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGT_FS      <CBR>           (Lop_BGT_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE         <CBR>           (Lop_BGE                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE_FS      <CBR>           (Lop_BGE_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT         <CBR>           (Lop_BLT                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT_FS      <CBR>           (Lop_BLT_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE         <CBR>           (Lop_BLE                 ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE_FS      <CBR>           (Lop_BLE_FS              ((IOI_cbr  RL_Branch  Lat1bb)) )
+
+	Lop_BGT_U       <CBR>           (Lop_BGT_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGT_U_FS    <CBR>           (Lop_BGT_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE_U       <CBR>           (Lop_BGE_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BGE_U_FS    <CBR>           (Lop_BGE_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT_U       <CBR>           (Lop_BLT_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLT_U_FS    <CBR>           (Lop_BLT_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE_U       <CBR>           (Lop_BLE_U               ((IOI_cbr  RL_Branch  Lat1bb)) )
+	Lop_BLE_U_FS    <CBR>           (Lop_BLE_U_FS            ((IOI_cbr  RL_Branch  Lat1bb)) )
+
+	Lop_BEQ_F       <CBR EXCEPT>    (Lop_BEQ_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BEQ_F_FS    <CBR EXCEPT>    (Lop_BEQ_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F       <CBR EXCEPT>    (Lop_BNE_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F_FS    <CBR EXCEPT>    (Lop_BNE_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F       <CBR EXCEPT>    (Lop_BGT_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F_FS    <CBR EXCEPT>    (Lop_BGT_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F       <CBR EXCEPT>    (Lop_BGE_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F_FS    <CBR EXCEPT>    (Lop_BGE_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F       <CBR EXCEPT>    (Lop_BLT_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F_FS    <CBR EXCEPT>    (Lop_BLT_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F       <CBR EXCEPT>    (Lop_BLE_F               ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F_FS    <CBR EXCEPT>    (Lop_BLE_F_FS            ((IOI_cbr  RL_Branch  Lat3bb)) )
+
+	Lop_BEQ_F2      <CBR EXCEPT>    (Lop_BEQ_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BEQ_F2_FS   <CBR EXCEPT>    (Lop_BEQ_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F2      <CBR EXCEPT>    (Lop_BNE_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BNE_F2_FS   <CBR EXCEPT>    (Lop_BNE_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F2      <CBR EXCEPT>    (Lop_BGT_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGT_F2_FS   <CBR EXCEPT>    (Lop_BGT_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F2      <CBR EXCEPT>    (Lop_BGE_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BGE_F2_FS   <CBR EXCEPT>    (Lop_BGE_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F2      <CBR EXCEPT>    (Lop_BLT_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLT_F2_FS   <CBR EXCEPT>    (Lop_BLT_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F2      <CBR EXCEPT>    (Lop_BLE_F2              ((IOI_cbr  RL_Branch  Lat3bb)) )
+	Lop_BLE_F2_FS   <CBR EXCEPT>    (Lop_BLE_F2_FS           ((IOI_cbr  RL_Branch  Lat3bb)) )
+
+# Integer ALU instructions
+
+	Lop_MOV	                        (Lop_MOV                 ((IOI_mov RL_IAlu  Lat1)) )
+	Lop_ABS	                        (Lop_ABS                 ((IOI_mov RL_IAlu  Lat1)) )
+	
+    	Lop_OR	                        (Lop_OR                  ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_AND	                        (Lop_AND                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_XOR	                        (Lop_XOR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_NOR	                        (Lop_NOR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_NAND                        (Lop_NAND                ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_NXOR                        (Lop_NXOR                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_OR_NOT                      (Lop_OR_NOT              ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_AND_NOT                     (Lop_AND_NOT             ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_OR_COMPL                    (Lop_OR_COMPL            ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_AND_COMPL                   (Lop_AND_COMPL           ((IOI_Std3  RL_IAlu  Lat1)) )
+
+	Lop_LSL	                        (Lop_LSL                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_LSR	                        (Lop_LSR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_ASR	                        (Lop_ASR                 ((IOI_Std3  RL_IAlu  Lat1)) )
+
+	Lop_ADD	                        (Lop_ADD                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_ADD_U                       (Lop_ADD_U               ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_SUB	                        (Lop_SUB                 ((IOI_Std3  RL_IAlu  Lat1)) )
+	Lop_SUB_U                       (Lop_SUB_U               ((IOI_Std3  RL_IAlu  Lat1)) )
+	
+				    
+# Integer comparison instructions
+
+    	Lop_EQ	                        (Lop_EQ                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_NE	                        (Lop_NE                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GT	                        (Lop_GT                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GT_U                        (Lop_GT_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GE	                        (Lop_GE                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_GE_U                        (Lop_GE_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LT	                        (Lop_LT                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LT_U                        (Lop_LT_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LE	                        (Lop_LE                  ((IOI_Std3  RL_IAlu  Lat1)) )
+    	Lop_LE_U                        (Lop_LE_U                ((IOI_Std3  RL_IAlu  Lat1)) )
+
+# Misc integer instructions
+
+	Lop_MUL	                     (Lop_MUL                 ((IOI_Std3  RL_IMul  Lat3)) )
+	Lop_MUL_U                    (Lop_MUL_U               ((IOI_Std3  RL_IMul  Lat3)) )
+	Lop_DIV	        <EXCEPT>        (Lop_DIV                 ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_DIV_U       <EXCEPT>        (Lop_DIV_U               ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_REM	        <EXCEPT>        (Lop_REM                 ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_REM_U       <EXCEPT>        (Lop_REM_U               ((IOI_Std3  RL_IDiv  Lat10)) )
+	Lop_MUL_ADD                     (Lop_MUL_ADD             ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_ADD_U                   (Lop_MUL_ADD_U           ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB                     (Lop_MUL_SUB             ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB_U                   (Lop_MUL_SUB_U           ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB_REV                 (Lop_MUL_SUB_REV         ((IOI_Std5  RL_IMul  Lat3)) )
+	Lop_MUL_SUB_REV_U               (Lop_MUL_SUB_REV_U       ((IOI_Std5  RL_IMul  Lat3)) )
+	
+# Floating point ALU instructions
+
+	Lop_MOV_F    		        (Lop_MOV_F               ((IOI_mov   RL_FPAlu  Lat1)) )
+	Lop_MOV_F2    		        (Lop_MOV_F2              ((IOI_mov   RL_FPAlu  Lat1)) )
+        Lop_ABS_F       <EXCEPT>        (Lop_ABS_F               ((IOI_mov   RL_FPAlu  Lat1)) )
+        Lop_ABS_F2      <EXCEPT>        (Lop_ABS_F2              ((IOI_mov   RL_FPAlu  Lat1)) )
+
+
+      	Lop_ADD_F       <EXCEPT>   	(Lop_ADD_F               ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_ADD_F2      <EXCEPT>   	(Lop_ADD_F2              ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_SUB_F       <EXCEPT>   	(Lop_SUB_F               ((IOI_Std3  RL_FPAlu  Lat3)) )
+      	Lop_SUB_F2      <EXCEPT>   	(Lop_SUB_F2              ((IOI_Std3  RL_FPAlu  Lat3)) )
+
+# Floating point comparison instructions
+
+	Lop_EQ_F        <EXCEPT>  	(Lop_EQ_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_EQ_F2       <EXCEPT>  	(Lop_EQ_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_NE_F        <EXCEPT>  	(Lop_NE_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_NE_F2       <EXCEPT>  	(Lop_NE_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GT_F        <EXCEPT>  	(Lop_GT_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GT_F2       <EXCEPT>  	(Lop_GT_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GE_F        <EXCEPT>  	(Lop_GE_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_GE_F2       <EXCEPT>  	(Lop_GE_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LT_F        <EXCEPT>  	(Lop_LT_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LT_F2       <EXCEPT>  	(Lop_LT_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LE_F        <EXCEPT>  	(Lop_LE_F                ((IOI_Std3  RL_FPAlu  Lat3)) )
+	Lop_LE_F2       <EXCEPT>  	(Lop_LE_F2               ((IOI_Std3  RL_FPAlu  Lat3)) )
+
+# Float point conversion instructions
+
+    	Lop_I_F	        <EXCEPT>	(Lop_I_F                 ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F_I	        <EXCEPT>	(Lop_F_I                 ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_I_F2        <EXCEPT>	(Lop_I_F2                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F2_I        <EXCEPT>	(Lop_F2_I                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F_F2        <EXCEPT>	(Lop_F_F2                ((IOI_mov   RL_FPAlu  Lat3)) )
+    	Lop_F2_F        <EXCEPT>	(Lop_F2_F                ((IOI_mov   RL_FPAlu  Lat3)) )
+
+# Misc floating point instructions 
+
+	Lop_MUL_F       <EXCEPT>	(Lop_MUL_F          	 ((IOI_Std3  RL_FPMul  Lat3)) )
+	Lop_MUL_F2      <EXCEPT>	(Lop_MUL_F2     	 ((IOI_Std3  RL_FPMul  Lat3)) )
+	Lop_DIV_F       <EXCEPT>	(Lop_DIV_F	         ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_DIV_F2      <EXCEPT>	(Lop_DIV_F2	         ((IOI_Std3  RL_FPDiv  Lat10)) )
+	Lop_MUL_ADD_F   <EXCEPT>        (Lop_MUL_ADD_F	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_ADD_F2  <EXCEPT>        (Lop_MUL_ADD_F2	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_F   <EXCEPT>        (Lop_MUL_SUB_F	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_REV_F  <EXCEPT>     (Lop_MUL_SUB_REV_F	 ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_F2  <EXCEPT>        (Lop_MUL_SUB_F2	         ((IOI_Std5  RL_FPMul  Lat3)) )
+	Lop_MUL_SUB_REV_F2 <EXCEPT>     (Lop_MUL_SUB_REV_F2	 ((IOI_Std5  RL_FPMul  Lat3)) )
+        Lop_SQRT_F       <EXCEPT>       (Lop_SQRT_F              ((IOI_Std3  RL_FPDiv  Lat10)) )
+        Lop_SQRT_F2      <EXCEPT>       (Lop_SQRT_F2             ((IOI_Std3  RL_FPDiv  Lat10)) )
+
+	
+# Load instructions
+
+	Lop_LD_UC	<LOAD EXCEPT>	(Lop_LD_UC               ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_UC	<LOAD EXCEPT>	(Lop_LD_PRE_UC           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_UC	<LOAD EXCEPT>	(Lop_LD_POST_UC          ((IOI_load2 RL_Load Lat2mb)) )
+
+	Lop_LD_C	<LOAD EXCEPT>	(Lop_LD_C                ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_C	<LOAD EXCEPT>	(Lop_LD_PRE_C            ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_C	<LOAD EXCEPT>	(Lop_LD_POST_C           ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_UC2	<LOAD EXCEPT>	(Lop_LD_UC2              ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_UC2	<LOAD EXCEPT>	(Lop_LD_PRE_UC2          ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_UC2	<LOAD EXCEPT>	(Lop_LD_POST_UC2         ((IOI_load2 RL_Load Lat2mb)) )
+
+	Lop_LD_C2	<LOAD EXCEPT>	(Lop_LD_C2               ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_C2	<LOAD EXCEPT>	(Lop_LD_PRE_C2           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_C2	<LOAD EXCEPT>	(Lop_LD_POST_C2          ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_I	<LOAD EXCEPT>	(Lop_LD_I                ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_I	<LOAD EXCEPT>	(Lop_LD_PRE_I            ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_I	<LOAD EXCEPT>	(Lop_LD_POST_I           ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_F	<LOAD EXCEPT>	(Lop_LD_F                ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_F	<LOAD EXCEPT>	(Lop_LD_PRE_F            ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_F	<LOAD EXCEPT>	(Lop_LD_POST_F           ((IOI_load2 RL_Load Lat2mb)) )
+	
+	Lop_LD_F2	<LOAD EXCEPT>	(Lop_LD_F2               ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_LD_PRE_F2	<LOAD EXCEPT>	(Lop_LD_PRE_F2           ((IOI_load2 RL_Load Lat2mb)) )
+	Lop_LD_POST_F2	<LOAD EXCEPT>	(Lop_LD_POST_F2          ((IOI_load2 RL_Load Lat2mb)) )
+	
+# Store instructions
+
+	Lop_ST_C	<STORE EXCEPT>	(Lop_ST_C                ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_C	<STORE EXCEPT>	(Lop_ST_PRE_C            ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_C	<STORE EXCEPT>	(Lop_ST_POST_C           ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_C2	<STORE EXCEPT>	(Lop_ST_C2               ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_C2	<STORE EXCEPT>	(Lop_ST_PRE_C2           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_C2	<STORE EXCEPT>	(Lop_ST_POST_C2          ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_I	<STORE EXCEPT>	(Lop_ST_I                ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_I	<STORE EXCEPT>	(Lop_ST_PRE_I            ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_I	<STORE EXCEPT>	(Lop_ST_POST_I           ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_F	<STORE EXCEPT>	(Lop_ST_F                ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_F	<STORE EXCEPT>	(Lop_ST_PRE_F            ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_F	<STORE EXCEPT>	(Lop_ST_POST_F           ((IOI_store2 RL_Store Lat1mb)) )
+	
+	Lop_ST_F2	<STORE EXCEPT>	(Lop_ST_F2               ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_ST_PRE_F2	<STORE EXCEPT>	(Lop_ST_PRE_F2           ((IOI_store2 RL_Store Lat1mb)) )
+	Lop_ST_POST_F2	<STORE EXCEPT>	(Lop_ST_POST_F2          ((IOI_store2 RL_Store Lat1mb)) )
+
+# Predicate setting instructions
+
+	Lop_PRED_CLEAR                  (Lop_PRED_CLEAR		 ((IOI_predclr RL_IAlu Lat1)) )
+	Lop_PRED_SET                    (Lop_PRED_SET		 ((IOI_predclr RL_IAlu Lat1)) )
+	Lop_PRED_COPY                   (Lop_PRED_COPY		 ((IOI_predcopy RL_IAlu Lat1)) )
+
+	Lop_PRED_LD	<LOAD EXCEPT>	(Lop_PRED_LD		 ((IOI_load1 RL_Load Lat2ma)) )
+	Lop_PRED_LD_BLK	<LOAD EXCEPT>	(Lop_PRED_LD_BLK	 ((IOI_load1 RL_Load Lat2ma)) )
+
+	Lop_PRED_ST	<STORE EXCEPT>	(Lop_PRED_ST		 ((IOI_store1 RL_Store Lat1ma)) )
+	Lop_PRED_ST_BLK	<STORE EXCEPT>	(Lop_PRED_ST_BLK	 ((IOI_store1 RL_Store Lat1ma)) )
+
+	Lop_PRED_EQ			(Lop_PRED_EQ		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_NE			(Lop_PRED_NE		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GT			(Lop_PRED_GT		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GT_U			(Lop_PRED_GT_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GE			(Lop_PRED_GE		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_GE_U			(Lop_PRED_GE_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LT			(Lop_PRED_LT		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LT_U			(Lop_PRED_LT_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LE			(Lop_PRED_LE		 ((IOI_predcmp RL_IAlu Lat1p)) )
+	Lop_PRED_LE_U			(Lop_PRED_LE_U		 ((IOI_predcmp RL_IAlu Lat1p)) )
+
+	Lop_PRED_EQ_F2	<EXCEPT>	(Lop_PRED_EQ_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_NE_F2	<EXCEPT>	(Lop_PRED_NE_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GT_F2	<EXCEPT>	(Lop_PRED_GT_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GE_F2	<EXCEPT>	(Lop_PRED_GE_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LT_F2	<EXCEPT>	(Lop_PRED_LT_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LE_F2	<EXCEPT>	(Lop_PRED_LE_F2		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+
+	Lop_PRED_EQ_F	<EXCEPT>	(Lop_PRED_EQ_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_NE_F	<EXCEPT>	(Lop_PRED_NE_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GT_F	<EXCEPT>	(Lop_PRED_GT_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_GE_F	<EXCEPT>	(Lop_PRED_GE_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LT_F	<EXCEPT>	(Lop_PRED_LT_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+	Lop_PRED_LE_F	<EXCEPT>	(Lop_PRED_LE_F		 ((IOI_predcmp RL_FPAlu Lat3p)) )
+
+	Lop_PRED_MASK_AND	  		(Lop_PRED_MASK_AND			((IOI_pred_mask_combine RL_INOP Lat0pc)) )
+	Lop_PRED_MASK_OR  			(Lop_PRED_MASK_OR			((IOI_pred_mask_combine RL_INOP Lat0pc)) )
+
+        Lop_CMOV                        (Lop_CMOV                ((IOI_cmov RL_IAlu  Lat1)) )
+        Lop_CMOV_COM                    (Lop_CMOV_COM            ((IOI_cmov RL_IAlu  Lat1)) )
+        Lop_CMOV_F                      (Lop_CMOV_F              ((IOI_cmov RL_FPAlu Lat1)) )
+        Lop_CMOV_COM_F                  (Lop_CMOV_COM_F          ((IOI_cmov RL_FPAlu Lat1)) )
+        Lop_CMOV_F2                     (Lop_CMOV_F2             ((IOI_cmov RL_FPAlu Lat1)) )
+        Lop_CMOV_COM_F2                 (Lop_CMOV_COM_F2         ((IOI_cmov RL_FPAlu Lat1)) )
+
+        Lop_SELECT                      (Lop_SELECT              ((IOI_select RL_IAlu  Lat1)) )
+        Lop_SELECT_F                    (Lop_SELECT_F            ((IOI_select RL_FPAlu Lat1)) )
+        Lop_SELECT_F2                   (Lop_SELECT_F2           ((IOI_select RL_FPAlu Lat1)) )
+
+end)
diff -urN openimpact-1.0rc4/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2
--- openimpact-1.0rc4/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2	1969-12-31 18:00:00.000000000 -0600
+++ openimpact-1.0rc4.Limpact/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2	2004-09-17 14:41:03.000000000 -0500
@@ -0,0 +1,90 @@
+/*****************************************************************************\
+ *
+ *		      Illinois Open Source License
+ *                     University of Illinois/NCSA
+ *                         Open Source License
+ *
+ * Copyright (c) 2004, The University of Illinois at Urbana-Champaign.
+ * All rights reserved.
+ *
+ * Developed by:             
+ *
+ *		IMPACT Research Group
+ *
+ *		University of Illinois at Urbana-Champaign
+ *
+ *              http://www.crhc.uiuc.edu/IMPACT
+ *              http://www.gelato.org
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal with the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimers.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimers in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the names of the IMPACT Research Group, the University of
+ * Illinois, nor the names of its contributors may be used to endorse
+ * or promote products derived from this Software without specific
+ * prior written permission.  THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
+ * LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+ * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS WITH THE SOFTWARE.
+ *
+\*****************************************************************************/
+/*****************************************************************************\
+ *
+ *  File:  IMPACT_SIMPLE_TEMPLATE.hmdes2
+ *
+ *  Description:  Simple machine description template for wide-variety of 
+ *                experimental processors that execute IMPACT's Lcode.
+ *                This simplified template does not model register ports and
+ *                uses a fairly simple function unit model.  It is designed
+ *                to be relatively easy to understand and modify.  
+ * 
+ *  Note: For hmdes2 documentation (slightly out-of-date), see:
+ * 
+ *          HMDES Version 2 Specification 
+ *          John C. Gyllenhaal, Wen-mei W. Hwu and B. Ramakrishna Rau
+ *          IMPACT Technical report, IMPACT-96-03, 
+ *          University of Illinois, Urbana IL. 1996.
+ *          http://www.crhc.uiuc.edu/IMPACT/ftp/report/impact-96-03.hmdes2.pdf
+ *
+ *  Note: Although IMPACT's and HPL's (Elcor) machine descriptions share a 
+ *        common host language "MD" (aka as "dabble" at HPL), they are not 
+ *        currently compatible with each other.  This machine description 
+ *        cannot be used with Trimaran's Elcor-based scheduler and Elcor's
+ *        machine descriptions cannot be used with IMPACT-based schedulers.
+ *        
+ *  Creation Date :  June 1999
+ *
+ *  Author:  John C. Gyllenhaal, Wen-mei Hwu
+ *
+ *  Revisions:
+ *
+\*****************************************************************************/
+
+/* 
+ * Processor resource configuration parameters. 
+ */
+
+$def WIDTH              8
+$def NUM_IALUS          ${WIDTH}
+$def NUM_FALUS          ${WIDTH}
+$def NUM_MEM_UNITS      ${WIDTH}
+$def NUM_BRANCHES       ${WIDTH}
+
+$include "${IMPACT_REL_PATH}/mdes/Limpact/IMPACT_BASE_TEMPLATE.hmdes2"
diff -urN openimpact-1.0rc4/mdes/Limpact/Makefile.am openimpact-1.0rc4.Limpact/mdes/Limpact/Makefile.am
--- openimpact-1.0rc4/mdes/Limpact/Makefile.am	1969-12-31 18:00:00.000000000 -0600
+++ openimpact-1.0rc4.Limpact/mdes/Limpact/Makefile.am	2003-01-22 09:00:52.000000000 -0600
@@ -0,0 +1,1439 @@
+## mdes/Limpact/Makefile.am
+## This file is (ultimately) included by the top level Makefile.am, so all
+## files need to be specified relative to the top level directory.
+
+## .lmdes2 file naming conventions:
+##
+##   EPIC_8G_2BL.lmdes2
+##      ^----------- Processor model (EPIC or SS)
+##        ^--------- Issue width (>= 1)
+##         ^-------- Percolation model (G or R)
+##           ^------ Branches per cycle ( >= 1 && <= issue width)
+##             ^---- Branches placement (L or X)
+##
+##
+##   Processor model:
+##
+##     EPIC -> EPIC processor.  The scheduler explicitly specifies what
+##             operations can be issued together (in parallel) and the
+##             processor's issue stage does exactly what it is told.
+##             This release's EPIC tools requires that branches to be
+##             placed last (L) in all EPIC operation packets. (This is
+##             not a significant restriction since if generating code
+##             for a real EPIC processor, you simply do a post-pass to
+##             rearrange the packet's operations into the desired
+##             order).
+##
+##     SS   -> Superscalar processor.  The scheduler explicitly
+##             specifies what operations can be issued together (in
+##             parallel) and the processor's issue stage *totally
+##             ignores* this information and dynamically decides what 
+##             to issue together each cycle.  Support for both the
+##             branches last (L) and branches anywhere (X) model.
+##             Note: Using the branches last model with SS creates an
+##             .lmdes2 file identical to the EPIC variation (the
+##             scheduled code can be simulated on either processor
+##             model).
+##
+##   Issue width:
+##
+##     int  -> The maximum number of operations that may be issued per
+##             cycle.
+##
+##   Percolation model:
+##
+##      G   -> General percolation.  Non-trapping (silent) versions of
+##             normally excepting operations (load, div, etc.) are
+##             available.  This allows aggressive code motion across
+##             branches, significantly increasing ILP.
+##	
+##      R   -> Restricted percolation.  No non-trapping operations.
+##             This restricts code motion across branches to those
+##             operations that can be proved to never throw an
+##             exception (except if it would in the original
+##             unoptimized code).
+##             Note: These .lmdes2 files only restricts the scheduler
+##             from generating non-trapping operations.  The optimizers
+##             (classical and ILP) also generates non-trapping
+##             operations if the Lglobal parameter
+##             non_excepting_ops == yes (default).  If you want *no*
+##             non-trapping operations, you must prevent them from
+##             being added by both the optimizers and the scheduler.
+##
+##   Branches per cycle:
+##
+##      int -> The maximum number of branches that may be issued per
+##             cycle.
+##
+##   Branch placement:
+##
+##      L   -> Branches last.  Branches are scheduled so they are last
+##             in each cycle's operation packet and no non-branches
+##             occur after a branch in the same cycle.  Required for
+##             EPIC and may be used for SS.
+##
+##      X   -> Branches anywhere.  Branches may occur anywhere in each
+##             cycle's operation packet.  These branches guard the
+##             the non-branch operations placed after it in the same
+##             cycle (prevent execution their execution, if the branch
+##             is taken).  Produces tighter schedules (since you
+##             effectively have a type of free predication on a few
+##             operations each cycle) but requires a more complex
+##             processor implementation.
+##
+
+mdes_Limpactdir = $(prefix)/mdes/Limpact
+
+mdes_Limpact_DATA = \
+	mdes/Limpact/EPIC_1G_1BL.lmdes2 mdes/Limpact/EPIC_2G_1BL.lmdes2 \
+	mdes/Limpact/EPIC_2G_2BL.lmdes2 mdes/Limpact/EPIC_4G_1BL.lmdes2 \
+	mdes/Limpact/EPIC_4G_2BL.lmdes2 mdes/Limpact/EPIC_4G_4BL.lmdes2 \
+	mdes/Limpact/EPIC_8G_1BL.lmdes2	mdes/Limpact/EPIC_8G_2BL.lmdes2 \
+	mdes/Limpact/EPIC_8G_4BL.lmdes2 mdes/Limpact/EPIC_8G_8BL.lmdes2 \
+	mdes/Limpact/EPIC_8G_1BL_TI.lmdes2 \
+	mdes/Limpact/EPIC_8G_MIX_3BX_LDLAT3.lmdes2 \
+	mdes/Limpact/EPIC_8G_MIX_3BX.lmdes2  mdes/Limpact/EPIC_16G_1BL.lmdes2 \
+	mdes/Limpact/EPIC_16G_2BL.lmdes2 mdes/Limpact/EPIC_16G_4BL.lmdes2 \
+	mdes/Limpact/EPIC_16G_8BL.lmdes2 mdes/Limpact/EPIC_16G_16BL.lmdes2 \
+	mdes/Limpact/EPIC_1R_1BL.lmdes2 mdes/Limpact/EPIC_2R_1BL.lmdes2 \
+	mdes/Limpact/EPIC_2R_2BL.lmdes2 mdes/Limpact/EPIC_4R_1BL.lmdes2 \
+	mdes/Limpact/EPIC_4R_2BL.lmdes2 mdes/Limpact/EPIC_4R_4BL.lmdes2 \
+	mdes/Limpact/EPIC_8R_1BL.lmdes2 mdes/Limpact/EPIC_8R_2BL.lmdes2 \
+	mdes/Limpact/EPIC_8R_4BL.lmdes2 mdes/Limpact/EPIC_8R_8BL.lmdes2 \
+	mdes/Limpact/EPIC_16R_16BL.lmdes2 mdes/Limpact/EPIC_16R_1BL.lmdes2 \
+	mdes/Limpact/EPIC_16R_2BL.lmdes2 mdes/Limpact/EPIC_16R_4BL.lmdes2 \
+	mdes/Limpact/EPIC_16R_8BL.lmdes2 \
+	mdes/Limpact/IMPACT_1G.lmdes mdes/Limpact/IMPACT_1G.lmdes2 \
+	mdes/Limpact/IMPACT_2G_1BR.lmdes mdes/Limpact/IMPACT_2G_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_2G.lmdes mdes/Limpact/IMPACT_2G.lmdes2 \
+	mdes/Limpact/IMPACT_3G_1BR.lmdes mdes/Limpact/IMPACT_3G_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_3G_2BR.lmdes mdes/Limpact/IMPACT_3G_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_3G.lmdes mdes/Limpact/IMPACT_3G.lmdes2 \
+	mdes/Limpact/IMPACT_4G_1BR.lmdes mdes/Limpact/IMPACT_4G_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_4G_2BR.lmdes mdes/Limpact/IMPACT_4G_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_4G.lmdes mdes/Limpact/IMPACT_4G.lmdes2 \
+	mdes/Limpact/IMPACT_8G_1BR.lmdes mdes/Limpact/IMPACT_8G_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_8G_2BR.lmdes mdes/Limpact/IMPACT_8G_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_8G_4BR.lmdes mdes/Limpact/IMPACT_8G_4BR.lmdes2 \
+	mdes/Limpact/IMPACT_8G.lmdes mdes/Limpact/IMPACT_8G.lmdes2 \
+	mdes/Limpact/IMPACT_16G_1BR.lmdes mdes/Limpact/IMPACT_16G_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_16G_2BR.lmdes mdes/Limpact/IMPACT_16G_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_16G_4BR.lmdes mdes/Limpact/IMPACT_16G_4BR.lmdes2 \
+	mdes/Limpact/IMPACT_16G_8BR.lmdes mdes/Limpact/IMPACT_16G_8BR.lmdes2 \
+	mdes/Limpact/IMPACT_16G.lmdes mdes/Limpact/IMPACT_16G.lmdes2 \
+	mdes/Limpact/IMPACT_1R.lmdes mdes/Limpact/IMPACT_1R.lmdes2 \
+	mdes/Limpact/IMPACT_2R_1BR.lmdes mdes/Limpact/IMPACT_2R_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_2R.lmdes mdes/Limpact/IMPACT_2R.lmdes2 \
+	mdes/Limpact/IMPACT_4R_1BR.lmdes mdes/Limpact/IMPACT_4R_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_4R_2BR.lmdes mdes/Limpact/IMPACT_4R_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_4R.lmdes mdes/Limpact/IMPACT_4R.lmdes2 \
+	mdes/Limpact/IMPACT_8R_1BR.lmdes mdes/Limpact/IMPACT_8R_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_8R_2BR.lmdes mdes/Limpact/IMPACT_8R_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_8R_4BR.lmdes mdes/Limpact/IMPACT_8R_4BR.lmdes2 \
+	mdes/Limpact/IMPACT_8R.lmdes mdes/Limpact/IMPACT_8R.lmdes2 \
+	mdes/Limpact/IMPACT_16R_1BR.lmdes mdes/Limpact/IMPACT_16R_1BR.lmdes2 \
+	mdes/Limpact/IMPACT_16R_2BR.lmdes mdes/Limpact/IMPACT_16R_2BR.lmdes2 \
+	mdes/Limpact/IMPACT_16R_4BR.lmdes mdes/Limpact/IMPACT_16R_4BR.lmdes2 \
+	mdes/Limpact/IMPACT_16R_8BR.lmdes mdes/Limpact/IMPACT_16R_8BR.lmdes2 \
+	mdes/Limpact/IMPACT_16R.lmdes mdes/Limpact/IMPACT_16R.lmdes2 \
+	mdes/Limpact/SS_1G_1BL.lmdes2 mdes/Limpact/SS_1G_1BX.lmdes2 \
+	mdes/Limpact/SS_2G_1BL.lmdes2 mdes/Limpact/SS_2G_1BX.lmdes2 \
+	mdes/Limpact/SS_2G_2BL.lmdes2 mdes/Limpact/SS_2G_2BX.lmdes2 \
+	mdes/Limpact/SS_4G_1BL.lmdes2 mdes/Limpact/SS_4G_1BX.lmdes2 \
+	mdes/Limpact/SS_4G_2BL.lmdes2 mdes/Limpact/SS_4G_2BX.lmdes2 \
+	mdes/Limpact/SS_4G_4BL.lmdes2 mdes/Limpact/SS_4G_4BX.lmdes2 \
+	mdes/Limpact/SS_8G_1BL.lmdes2 mdes/Limpact/SS_8G_1BX.lmdes2 \
+	mdes/Limpact/SS_8G_2BL.lmdes2 mdes/Limpact/SS_8G_2BX.lmdes2 \
+	mdes/Limpact/SS_8G_4BL.lmdes2 mdes/Limpact/SS_8G_4BX.lmdes2 \
+	mdes/Limpact/SS_8G_8BL.lmdes2 mdes/Limpact/SS_8G_8BX.lmdes2 \
+	mdes/Limpact/SS_16G_1BL.lmdes2 mdes/Limpact/SS_16G_1BX.lmdes2 \
+	mdes/Limpact/SS_16G_2BL.lmdes2 mdes/Limpact/SS_16G_2BX.lmdes2 \
+	mdes/Limpact/SS_16G_4BL.lmdes2 mdes/Limpact/SS_16G_4BX.lmdes2 \
+	mdes/Limpact/SS_16G_8BL.lmdes2 mdes/Limpact/SS_16G_8BX.lmdes2 \
+	mdes/Limpact/SS_16G_16BL.lmdes2 mdes/Limpact/SS_16G_16BX.lmdes2 \
+	mdes/Limpact/SS_1R_1BL.lmdes2 mdes/Limpact/SS_1R_1BX.lmdes2 \
+	mdes/Limpact/SS_2R_1BL.lmdes2 mdes/Limpact/SS_2R_1BX.lmdes2 \
+	mdes/Limpact/SS_2R_2BL.lmdes2 mdes/Limpact/SS_2R_2BX.lmdes2 \
+	mdes/Limpact/SS_4R_1BL.lmdes2 mdes/Limpact/SS_4R_1BX.lmdes2 \
+	mdes/Limpact/SS_4R_2BL.lmdes2 mdes/Limpact/SS_4R_2BX.lmdes2 \
+	mdes/Limpact/SS_4R_4BL.lmdes2 mdes/Limpact/SS_4R_4BX.lmdes2 \
+	mdes/Limpact/SS_8R_1BL.lmdes2 mdes/Limpact/SS_8R_1BX.lmdes2 \
+	mdes/Limpact/SS_8R_2BL.lmdes2 mdes/Limpact/SS_8R_2BX.lmdes2 \
+	mdes/Limpact/SS_8R_4BL.lmdes2 mdes/Limpact/SS_8R_4BX.lmdes2 \
+	mdes/Limpact/SS_8R_8BL.lmdes2 mdes/Limpact/SS_8R_8BX.lmdes2 \
+	mdes/Limpact/SS_16R_1BL.lmdes2 mdes/Limpact/SS_16R_1BX.lmdes2 \
+	mdes/Limpact/SS_16R_2BL.lmdes2 mdes/Limpact/SS_16R_2BX.lmdes2 \
+	mdes/Limpact/SS_16R_4BL.lmdes2 mdes/Limpact/SS_16R_4BX.lmdes2 \
+	mdes/Limpact/SS_16R_8BL.lmdes2 mdes/Limpact/SS_16R_8BX.lmdes2 \
+	mdes/Limpact/SS_16R_16BL.lmdes2 mdes/Limpact/SS_16R_16BX.lmdes2
+dist_mdes_Limpact_DATA = mdes/Limpact/EPIC_8G_1BL_TI.hmdes2 \
+			 mdes/Limpact/IMPACT_BASE_TEMPLATE.hmdes2 \
+			 mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+			 mdes/Limpact/IMPACT_GEN_NEWPRED_BASE.hmdes \
+			 mdes/Limpact/IMPACT_IA64_TEMPLATE.hmdes2 \
+			 mdes/Limpact/IMPACT_RES_BASE.hmdes \
+			 mdes/Limpact/IMPACT_RES_NEWPRED_BASE.hmdes \
+			 mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+			 mdes/Limpact/PACT_BASE_TEMPLATE.hmdes2 \
+			 mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2
+
+## Specify the files that are created by this make file so that 'make clean'
+## will delete them properly.
+mdes_Limpact_CLN = $(mdes_Limpact_DATA)
+
+## A target to support building everything under this subdirectory.  This
+## should refer to anything defined above.  There should be two targets; one
+## with and one without the trailing slash.  The trailing slash will allow
+## the use of tab completion.
+mdes/Limpact mdes/Limpact/: $(mdes_Limpact_DATA)
+
+## A target to support cleaning everything under this subdirectory.
+mdes/Limpact/clean:
+	rm -f $(mdes_Limpact_CLN)
+
+mdes/Limpact/EPIC_1G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_1G_1BL.lmdes2 -DWIDTH=1 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_2G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_2G_1BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_2G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_2G_2BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_4G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_4G_1BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_4G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_4G_2BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_4G_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_4G_4BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_8G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_1BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_8G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_2BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_8G_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_4BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_8G_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_8BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+# Build separate TI `C6x-based EPIC MIX    MCM 2/2000
+mdes/Limpact/EPIC_8G_1BL_TI.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/EPIC_8G_1BL_TI.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/EPIC_8G_1BL_TI.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_1BL_TI.lmdes2 -DWIDTH=8
+
+# Build Itanium-like EPIC MIX MCM 3/2001
+mdes/Limpact/EPIC_8G_MIX_3BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_MIX_3BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=3 -DNUM_IALUS=5 -DNUM_FALUS=3 -DNUM_DIVS=1 \
+		-DNUM_MEM_UNITS=3 -DNUM_CHK=8 -DBRANCHES_AT_END=0 \
+		-DNON_TRAPPING_OPS=1 -DLOAD_LAT=2
+
+# Build Itanium-like EPIC MIX MCM 3/2001
+mdes/Limpact/EPIC_8G_MIX_3BX_LDLAT3.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8G_MIX_3BX_LDLAT3.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=3 -DNUM_IALUS=5 -DNUM_FALUS=3 -DNUM_DIVS=1 \
+		-DNUM_MEM_UNITS=3 -DNUM_CHK=8 -DBRANCHES_AT_END=0 \
+		-DNON_TRAPPING_OPS=1 -DLOAD_LAT=3
+
+mdes/Limpact/EPIC_16G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16G_1BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_16G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16G_2BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_16G_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16G_4BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_16G_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16G_8BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_16G_16BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16G_16BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=16 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/EPIC_1R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_1R_1BL.lmdes2 -DWIDTH=1 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_2R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_2R_1BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_2R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_2R_2BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_4R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_4R_1BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_4R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_4R_2BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_4R_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_4R_4BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_8R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8R_1BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_8R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8R_2BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_8R_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8R_4BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_8R_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_8R_8BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_16R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16R_1BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_16R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16R_2BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_16R_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16R_4BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_16R_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16R_8BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/EPIC_16R_16BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/EPIC_16R_16BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=16 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+# WARNING - ISSUE rates and BRANCH rates are zero relative!!!!
+# general percolation models
+mdes/Limpact/IMPACT_1G.lmdes mdes/Limpact/IMPACT_1G.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_1G.lmdes -DISSUE=0 -DBRANCH=0
+
+mdes/Limpact/IMPACT_2G_1BR.lmdes mdes/Limpact/IMPACT_2G_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_2G_1BR.lmdes -DISSUE=1 -DBRANCH=0
+
+mdes/Limpact/IMPACT_2G.lmdes mdes/Limpact/IMPACT_2G.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_2G.lmdes -DISSUE=1 -DBRANCH=1
+
+mdes/Limpact/IMPACT_3G_1BR.lmdes mdes/Limpact/IMPACT_3G_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_3G_1BR.lmdes -DISSUE=2 -DBRANCH=0
+
+mdes/Limpact/IMPACT_3G_2BR.lmdes mdes/Limpact/IMPACT_3G_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_3G_2BR.lmdes -DISSUE=2 -DBRANCH=1
+
+mdes/Limpact/IMPACT_3G.lmdes mdes/Limpact/IMPACT_3G.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_3G.lmdes -DISSUE=2 -DBRANCH=2
+
+mdes/Limpact/IMPACT_4G_1BR.lmdes mdes/Limpact/IMPACT_4G_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_4G_1BR.lmdes -DISSUE=3 -DBRANCH=0
+
+mdes/Limpact/IMPACT_4G_2BR.lmdes mdes/Limpact/IMPACT_4G_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_4G_2BR.lmdes -DISSUE=3 -DBRANCH=1
+
+mdes/Limpact/IMPACT_4G.lmdes mdes/Limpact/IMPACT_4G.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_4G.lmdes -DISSUE=3 -DBRANCH=3
+
+mdes/Limpact/IMPACT_8G_1BR.lmdes mdes/Limpact/IMPACT_8G_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_8G_1BR.lmdes -DISSUE=7 -DBRANCH=0
+
+mdes/Limpact/IMPACT_8G_2BR.lmdes mdes/Limpact/IMPACT_8G_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_8G_2BR.lmdes -DISSUE=7 -DBRANCH=1
+
+mdes/Limpact/IMPACT_8G_4BR.lmdes mdes/Limpact/IMPACT_8G_4BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_8G_4BR.lmdes -DISSUE=7 -DBRANCH=3
+
+mdes/Limpact/IMPACT_8G.lmdes mdes/Limpact/IMPACT_8G.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_8G.lmdes -DISSUE=7 -DBRANCH=7
+
+
+mdes/Limpact/IMPACT_16G_1BR.lmdes mdes/Limpact/IMPACT_16G_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_16G_1BR.lmdes -DISSUE=15 -DBRANCH=0
+
+mdes/Limpact/IMPACT_16G_2BR.lmdes mdes/Limpact/IMPACT_16G_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_16G_2BR.lmdes -DISSUE=15 -DBRANCH=1
+
+mdes/Limpact/IMPACT_16G_4BR.lmdes mdes/Limpact/IMPACT_16G_4BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_16G_4BR.lmdes -DISSUE=15 -DBRANCH=3
+
+mdes/Limpact/IMPACT_16G_8BR.lmdes mdes/Limpact/IMPACT_16G_8BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_16G_8BR.lmdes -DISSUE=15 -DBRANCH=7
+
+mdes/Limpact/IMPACT_16G.lmdes mdes/Limpact/IMPACT_16G.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_GEN_BASE.hmdes \
+		mdes/Limpact/IMPACT_16G.lmdes -DISSUE=15 -DBRANCH=15
+
+# restricted percolation models
+mdes/Limpact/IMPACT_1R.lmdes mdes/Limpact/IMPACT_1R.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_1R.lmdes -DISSUE=0 -DBRANCH=0
+
+mdes/Limpact/IMPACT_2R_1BR.lmdes mdes/Limpact/IMPACT_2R_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_2R_1BR.lmdes -DISSUE=1 -DBRANCH=0
+
+mdes/Limpact/IMPACT_2R.lmdes mdes/Limpact/IMPACT_2R.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_2R.lmdes -DISSUE=1 -DBRANCH=1
+
+mdes/Limpact/IMPACT_4R_1BR.lmdes mdes/Limpact/IMPACT_4R_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_4R_1BR.lmdes -DISSUE=3 -DBRANCH=0
+
+mdes/Limpact/IMPACT_4R_2BR.lmdes mdes/Limpact/IMPACT_4R_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_4R_2BR.lmdes -DISSUE=3 -DBRANCH=1
+
+mdes/Limpact/IMPACT_4R.lmdes mdes/Limpact/IMPACT_4R.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_4R.lmdes -DISSUE=3 -DBRANCH=3
+
+mdes/Limpact/IMPACT_8R_1BR.lmdes mdes/Limpact/IMPACT_8R_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_8R_1BR.lmdes -DISSUE=7 -DBRANCH=0
+
+mdes/Limpact/IMPACT_8R_2BR.lmdes mdes/Limpact/IMPACT_8R_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_8R_2BR.lmdes -DISSUE=7 -DBRANCH=1
+
+mdes/Limpact/IMPACT_8R_4BR.lmdes mdes/Limpact/IMPACT_8R_4BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_8R_4BR.lmdes -DISSUE=7 -DBRANCH=3
+
+mdes/Limpact/IMPACT_8R.lmdes mdes/Limpact/IMPACT_8R.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_8R.lmdes -DISSUE=7 -DBRANCH=7
+
+mdes/Limpact/IMPACT_16R_1BR.lmdes mdes/Limpact/IMPACT_16R_1BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_16R_1BR.lmdes -DISSUE=15 -DBRANCH=0
+
+mdes/Limpact/IMPACT_16R_2BR.lmdes mdes/Limpact/IMPACT_16R_2BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_16R_2BR.lmdes -DISSUE=15 -DBRANCH=1
+
+mdes/Limpact/IMPACT_16R_4BR.lmdes mdes/Limpact/IMPACT_16R_4BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_16R_4BR.lmdes -DISSUE=15 -DBRANCH=3
+
+mdes/Limpact/IMPACT_16R_8BR.lmdes mdes/Limpact/IMPACT_16R_8BR.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_16R_8BR.lmdes -DISSUE=15 -DBRANCH=7
+
+mdes/Limpact/IMPACT_16R.lmdes mdes/Limpact/IMPACT_16R.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/Lmdes_build bin/md_preprocessor bin/md_compiler \
+		bin/lmdes2_customizer bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	Lmdes_build2 $(abs_srcdir)/mdes/Limpact/IMPACT_RES_BASE.hmdes \
+		mdes/Limpact/IMPACT_16R.lmdes -DISSUE=15 -DBRANCH=15
+
+mdes/Limpact/SS_1G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_1G_1BL.lmdes2 -DWIDTH=1 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_1G_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_1G_1BX.lmdes2 -DWIDTH=1 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_2G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2G_1BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_2G_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2G_1BX.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_2G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2G_2BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_2G_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2G_2BX.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_4G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4G_1BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_4G_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4G_1BX.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_4G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4G_2BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_4G_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4G_2BX.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_4G_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4G_4BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_4G_4BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4G_4BX.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_1BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_1BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_2BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_2BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_4BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_4BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_4BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_8BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_8G_8BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8G_8BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_1BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_1BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_2BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_2BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_4BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_4BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_4BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_8BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_8BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_8BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_16BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_16BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=16 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_16G_16BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16G_16BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=16 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=1
+
+mdes/Limpact/SS_1R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_1R_1BL.lmdes2 -DWIDTH=1 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_1R_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_1R_1BX.lmdes2 -DWIDTH=1 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_2R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2R_1BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_2R_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2R_1BX.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_2R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2R_2BL.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_2R_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_2R_2BX.lmdes2 -DWIDTH=2 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_4R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4R_1BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_4R_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4R_1BX.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_4R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4R_2BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_4R_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4R_2BX.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_4R_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4R_4BL.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_4R_4BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_4R_4BX.lmdes2 -DWIDTH=4 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_1BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_1BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_2BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_2BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_4BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_4BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_4BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_8BL.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_8R_8BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_8R_8BX.lmdes2 -DWIDTH=8 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_1BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_1BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_1BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_1BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=1 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_2BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_2BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_2BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_2BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=2 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_4BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_4BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_4BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_4BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=4 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_8BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_8BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_8BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_8BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=8 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_16BL.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_16BL.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=16 -DBRANCHES_AT_END=1 -DNON_TRAPPING_OPS=0
+
+mdes/Limpact/SS_16R_16BX.lmdes2: \
+		$(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		$(top_builddir)/mdes/structure/structure_IMPACT.ho \
+		bin/md_preprocessor bin/md_compiler bin/lmdes2_customizer \
+		bin/convert_hmdes
+	mkdir -p mdes/Limpact
+	hmdesc $(abs_srcdir)/mdes/Limpact/IMPACT_SIMPLE_TEMPLATE.hmdes2 \
+		-o mdes/Limpact/SS_16R_16BX.lmdes2 -DWIDTH=16 \
+		-DNUM_BRANCHES=16 -DBRANCHES_AT_END=0 -DNON_TRAPPING_OPS=0
+
+
+
+
+
+
+
+
diff -urN openimpact-1.0rc4/mdes/Limpact/PACT_BASE_TEMPLATE.hmdes2 openimpact-1.0rc4.Limpact/mdes/Limpact/PACT_BASE_TEMPLATE.hmdes2
--- openimpact-1.0rc4/mdes/Limpact/PACT_BASE_TEMPLATE.hmdes2	1969-12-31 18:00:00.000000000 -0600
+++ openimpact-1.0rc4.Limpact/mdes/Limpact/PACT_BASE_TEMPLATE.hmdes2	2004-09-17 14:41:04.000000000 -0500
@@ -0,0 +1,918 @@
+/*****************************************************************************\
+ *
+ *		      Illinois Open Source License
+ *                     University of Illinois/NCSA
+ *                         Open Source License
+ *
+ * Copyright (c) 2004, The University of Illinois at Urbana-Champaign.
+ * All rights reserved.
+ *
+ * Developed by:             
+ *
+ *		IMPACT Research Group
+ *
+ *		University of Illinois at Urbana-Champaign
+ *
+ *              http://www.crhc.uiuc.edu/IMPACT
+ *              http://www.gelato.org
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal with the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimers.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimers in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the names of the IMPACT Research Group, the University of
+ * Illinois, nor the names of its contributors may be used to endorse
+ * or promote products derived from this Software without specific
+ * prior written permission.  THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
+ * LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+ * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS WITH THE SOFTWARE.
+ *
+\*****************************************************************************/
+/*****************************************************************************\
+ *
+ *  File:  IMPACT_SIMPLE_TEMPLATE.hmdes2
+ *
+ *  Description:  Simple machine description template for wide-variety of 
+ *                experimental processors that execute IMPACT's Lcode.
+ *                This simplified template does not model register ports and
+ *                uses a fairly simple function unit model.  It is designed
+ *                to be relatively easy to understand and modify.  
+ * 
+ *  Note: For hmdes2 documentation (slightly out-of-date), see:
+ * 
+ *          HMDES Version 2 Specification 
+ *          John C. Gyllenhaal, Wen-mei W. Hwu and B. Ramakrishna Rau
+ *          IMPACT Technical report, IMPACT-96-03, 
+ *          University of Illinois, Urbana IL. 1996.
+ *          http://www.crhc.uiuc.edu/IMPACT/ftp/report/impact-96-03.hmdes2.pdf
+ *
+ *  Note: Although IMPACT's and HPL's (Elcor) machine descriptions share a 
+ *        common host language "MD" (aka as "dabble" at HPL), they are not 
+ *        currently compatible with each other.  This machine description 
+ *        cannot be used with Trimaran's Elcor-based scheduler and Elcor's
+ *        machine descriptions cannot be used with IMPACT-based schedulers.
+ *        
+ *  Creation Date :  June 1999
+ *
+ *  Author:  John C. Gyllenhaal, Wen-mei Hwu
+ *
+ *  Revisions:
+ *
+\*****************************************************************************/
+
+/* Read in the IMPACT's expected structure for this .hmdes2 file */
+$include "${IMPACT_REL_PATH}/mdes/structure/structure_IMPACT.hmdes2"
+
+/* 
+ * Processor resource configuration parameters. 
+ */
+
+$def WIDTH              8
+$def NUM_IALUS          ${WIDTH}
+$def NUM_FALUS          ${WIDTH}
+$def NUM_DIVS           ${WIDTH}
+$def NUM_MEM_UNITS      ${WIDTH}
+$def NUM_BRANCHES       ${WIDTH}
+$def NUM_CHK            ${WIDTH}
+$def LOAD_LAT		2
+
+/*
+ * Cycle in which UBR / CBR load source predicate.  Setting to 1 instead
+ * of 0 yields a 0-cycle-delay between pred defines and branches.
+ */
+$def PBDELAY            1
+
+/* 
+ * Processor issue-rule configuration parameters. 
+ */
+$def BRANCHES_AT_END    1  // If 1, places branches at end of each instr packet
+$def NON_TRAPPING_OPS   1  // If 1, allow general speculation
+
+
+/* 
+ * Scheduling 'slots' are used by the scheduler to determine ordering of 
+ * operations within an operation packet (operations scheduled to execute 
+ * in the same cycle).  The 'decoder' resources are used by this machine
+ * description to set the maximum number of operations that can be issued 
+ * per cycle (WIDTH).  The 'branch' resources are used by this
+ * machine description to set the maximum number of branches that can
+ * be issued per cycle (NUM_BRANCHES).
+ *
+ * If there are no constraints on operation ordering within the packet
+ * (i.e., branches can be scheduled anywhere), we will create the same
+ * number of slots as decoders.  
+ *
+ *   Example SS_3G_2BX (3-issue, 2 branches anywhere):
+ *          slot0: any operation (branch or non-branch)
+ *          slot1: any operation 
+ *          slot2: any operation 
+ *       decoder1: any operation
+ *       decoder2: any operation
+ *       decoder3: any operation
+ *        branch1: any branch
+ *        branch2: any branch
+ *
+ *
+ * If branches must be placed at the end, but there is only one branch,
+ * we still create the same number of slots as decoders and just
+ * require branches to use the last slot.
+ *
+ *   Example SS_3G_1BL (3-issue, 1 branch last):
+ *          slot0: non-branch operation 
+ *          slot1: non-branch operation 
+ *          slot2: any operation 
+ *       decoder1: any operation
+ *       decoder2: any operation
+ *       decoder3: any operation
+ *        branch1: any branch
+ *
+ * If branches must be placed at the end, but there are more than one branch,
+ * we need to create more slots than decoders, in order to force branches
+ * to the end.  Although there are more slots in this case, the decoders
+ * still limit the operations per cycle (to WIDTH).
+ *
+ *   Example SS_3G_2BL (3-issue, 2 branches last):
+ *          slot0: non-branch operation   <- add1
+ *          slot1: non-brancH operation   <- (not used)
+ *          slot2: any operation          <- branch1
+ *          slot3: branch operation       <- branch2
+ *       decoder1: any operation          <- add1
+ *       decoder2: any operation          <- branch1
+ *       decoder3: any operation          <- branch2
+ *        branch1: any branch             <- branch1
+ *        branch2: any branch             <- branch2
+ *
+ *  Example of why using the same number of slots does not work for SS_3G_2BL:
+ *          slot0: non-branch operation   <- add1
+ *          slot1: any operation          <- branch1
+ *          slot2: any operation          <- add2    (*not allowed*)
+ *       decoder1: any operation          <- add1
+ *       decoder2: any operation          <- branch1
+ *       decoder3: any operation          <- add2
+ *        branch1: any branch             <- branch1
+ *        branch2: any branch             <- (not used)
+ * 
+ * In the SS_3G_2BL example, it is *still* a three issue processor even
+ * though it has four issue slots!
+ *
+ * For historical reasons, the scheduler tools expect the slots to be
+ * numbered slot0,...slotN.
+ */
+$if (${BRANCHES_AT_END} == 1)
+{
+    /* Create the minimum number of slots that allow us to force
+     * branches to the end of the operation packet.
+     */
+    $def LAST_SLOT $={ (${WIDTH}-1) + (${NUM_BRANCHES}-1) }
+}
+$else
+{
+    /* Otherwise, just create one slot per decoder */
+    $def LAST_SLOT $={${WIDTH}-1}
+}
+
+
+/* Section for passing parameters to IMPACT's scheduler and 
+ * lmdes2_customizer 
+ */
+SECTION Parameter
+{
+  /* Used by lmdes2_customizer to assign integer numbers to many of the
+   * strings in this machine description, such as Lop_ADD, Label, REG
+   * EXCEPT, LOAD, etc.
+   */
+  customization_headers
+                (value("${IMPACT_ROOT}/include/Lcode/l_opc.h"
+                       "${IMPACT_ROOT}/include/Lcode/l_flags.h"
+                       "${IMPACT_ROOT}/include/Lcode/limpact_phase1.h"
+                       "${IMPACT_ROOT}/include/machine/m_spec.h"
+                       "${IMPACT_ROOT}/include/machine/m_impact.h"));
+
+  /* Phased out in version 2.31, but should always be set to "superscalar" 
+   * for backward compatibilty and so lmdes2_customizer does not complain.
+   * It is OK to set this to superscalar when targeting an EPIC processor!
+   */
+  processor_model (value("superscalar"));
+
+}
+
+/* Convert the scheduler operand types (NULL, p, i, f, f2, Label, and Lit)
+ * into the short name (A) that will be used to describe 
+ * the operation format mapping entries in Operation_Format.
+ */
+SECTION Field_Type
+{
+  /* Names the scheduler (thru Mspec) will use to describe the operands */
+  NULL ();                              // No operand allowed
+  p ();                                 // Predicate register operand 
+  i ();                                 // Integer register operand 
+  f ();                                 // Float register operand 
+  f2 ();                                // Double register operand 
+  Label ();                             // Generic label literal
+  Lit ();			        // Generic non-label literal
+  REG (compatible_with (i f f2));      // Generic register operand
+
+  /* Remap and group the names above into one letter names for ease of use 
+   * below in Operation Format.  Since not modeling register port usage
+   * in this template, just map everything to 'A'.
+   */
+  A (compatible_with (NULL p i f f2 Label Lit REG)); // Anything allowed
+}
+
+/* Define all the operation formats supported in the target machine.
+ *
+ * All entrys are in the form:
+ *   P0_D0D1_S0S1S2  
+ *
+ * where:
+ *   P0       is the pred[0] operand specifier 
+ *   D0       is the dest[0] operand specifier 
+ *   D1       is the dest[1] operand specifier 
+ *   S0       is the src[0] operand specifier 
+ *   S1       is the src[1] operand specifier 
+ *   S2       is the src[2] operand specifier 
+ *   
+ * Since in this template, we are not modeling register port usage, only
+ * one operation format is needed (significantly simplifying the rest of
+ * the machine description).
+ */
+SECTION Operation_Format
+{
+  A_AAAA_AAAAAA                       (pred (A) dest (A A A A) src (A A A A A A));
+}
+
+
+/*
+ *  Declare the processor resources that we wish to model.
+ *
+ *  Note: The resource names (such as decoder1) are *not* keywords.
+ *        Renaming all the resources to r1, r2, r3... r30 (and 
+ *        their references) will yield the exact same schedule.
+ *
+ *  Note: You can use as many or few resources as desired in order
+ *        to model the processor's execution constraints.  Typically,
+ *        we don't model anything that doesn't add execution constraints
+ *        (e.g., pipeline stages in fully-pipelined function units, etc.).
+ *         
+ *
+ *  Note: The 'slot' field is used to associate slot ids with particular
+ *        resource names.  For simplicity, we assign slot id 0, to slot0,
+ *        etc.  Not defining the 'slot' field indicates that this is 
+ *        a non-slot (i.e., normal) resource.
+ *        For example, to associate scheduler slot 3, with resource 
+ *        'my_slot_3':
+ *           my_slot_3 (slot(3));
+ */
+SECTION Resource
+{
+  /* Slots are used to control how operations are scheduled within the
+   * same cycle (instruction packet).  For historical reasons, slots
+   * are numbered starting from 0 (the first slot in the packet).
+   */
+  $for (I in $0..${LAST_SLOT})
+  {
+      slot${I} (slot(${I}));
+  }
+
+  /* Decoders are used to limit the number of operations that can
+   * issue in one cycle.
+   */
+  $for (I in $1..${WIDTH})
+  {
+      decoder${I} ();
+  }
+
+  /* Create the various functional units for this machine
+   * Note: All these units are assumed to be fully pipelined, so
+   *       we only need to model the first stage.
+   */
+  $for (I in $1..${NUM_IALUS})
+  {
+      ialu${I} ();
+  }
+
+  $for (I in $1..${NUM_CHK})
+  {
+      chk${I} ();
+  }
+
+  $for (I in $1..${NUM_FALUS})
+  {
+      falu${I} ();
+  }
+
+  $for (I in $1..${NUM_DIVS})
+  {
+      div${I} ();
+  } 
+
+  $for (I in $1..${NUM_BRANCHES})
+  {
+      branch${I} ();
+  }
+
+  $for (I in $1..${NUM_MEM_UNITS})
+  {
+      mem${I} ();
+  }
+}
+
+/*
+ * Specify the possible times in the pipeline the resources can be 
+ * used.  Here is the time mapping used in this machine description
+ * for resource usages:
+ * 
+ *   0 -> Fetch stage
+ *   1 -> Decode stage
+ *   2 -> First execution stage
+ *   3 -> Second execution stage and write-back stage for latency 1 ops
+ *   4 -> Third execution stage and write-back stage for latency 2 ops
+ *   etc.
+ */
+SECTION Resource_Usage
+{
+
+  /*
+   * Fetch stage
+   */    
+  $for (I in $0..${LAST_SLOT})
+  {
+      RU_slot${I}_t0_0 (use(slot${I}) time (0));
+  }
+
+
+  /*
+   * Decoder stage
+   */
+  $for (I in $1..${WIDTH})
+  {
+      RU_decoder${I}_t1_1 (use(decoder${I}) time (1));
+  }
+
+
+  /*
+   * First execution stage
+   */
+  $for (I in $1..${NUM_IALUS})
+  {
+      RU_ialu${I}_t2_2 (use(ialu${I}) time (2));
+  }
+
+  $for (I in $1..${NUM_CHK})
+  {
+      RU_chk${I}_t2_2 (use(chk${I}) time (2));
+  }
+
+  $for (I in $1..${NUM_FALUS})
+  {
+      RU_falu${I}_t2_2 (use(falu${I}) time (2));
+  }
+
+  $for (I in $1..${NUM_DIVS})
+  {
+      RU_div${I}_t2_2 (use(div${I}) time (2));
+  }	
+
+  $for (I in $1..${NUM_BRANCHES})
+  {
+      RU_branch${I}_t2_2 (use(branch${I}) time (2));
+  }
+
+  $for (I in $1..${NUM_MEM_UNITS})
+  {
+      RU_mem${I}_t2_2 (use(mem${I}) time (2));
+  }
+
+  /*
+   * Second execution stage and write-back stage for latency 1 ops
+   * etc.
+   */
+  /*
+   * We are assuming fully-pipelined functional units, so later
+   * stages do not need to be modeled.  We are not modeling register
+   * ports, so the write-backs don't need to be modeled.
+   */
+}
+
+/* Group together resource usages that should always be used together.
+ * None necessary for this simplified machine description.
+ */
+SECTION Resource_Unit
+{ 
+}
+
+/* Create options where any one of the options may be selected.
+ * For example, any one of the declared IALUs may be used.
+ *
+ * Note: Table options are used to create the OR part of AND/OR-trees.
+ */
+SECTION Table_Option
+{
+  /* Use any "normal" slot for non-branch operations. */
+  any_normal_slot_t0_0 
+  (
+      one_of($for (I in $0..(${WIDTH}-1)) {RU_slot${I}_t0_0 })
+  );
+
+  /* If placing branches at end, branches can only use the last normal
+   * slot and the extra slots after the normal slots (if 2 or more branches).
+   */
+  $if (${BRANCHES_AT_END} == 1)
+  {
+      any_branch_slot_t0_0
+      (
+          one_of($for (I in $(${WIDTH}-1)..${LAST_SLOT}){RU_slot${I}_t0_0 })
+      );
+  }
+  /* Otherwise, can place branch in any normal slot, just like non-branch ops*/
+  $else
+  {
+      any_branch_slot_t0_0 
+      (
+          one_of($for (I in $0..(${WIDTH}-1)) {RU_slot${I}_t0_0 })
+      );
+  }
+
+  /* 
+   * Allow any of the decoders to be used. 
+   * This resource use limits the processor's issue width, not slots.
+   */
+  any_decoder_t1_1 
+  (
+      one_of($for (I in $1..${WIDTH}){RU_decoder${I}_t1_1 })
+  );
+
+  /* 
+   * Allow any of the declared functional units to be used 
+   */
+  any_ialu_t2_2 
+  (
+      one_of($for (I in $1..${NUM_IALUS}) {RU_ialu${I}_t2_2 })
+  );
+
+  any_chk_t2_2
+  (
+      one_of($for (I in $1..${NUM_CHK}) {RU_chk${I}_t2_2 })
+  );
+
+  any_falu_t2_2 
+  (
+      one_of($for (I in $1..${NUM_FALUS}) {RU_falu${I}_t2_2 })
+  );
+
+  any_div_t2_2
+  (
+      one_of($for (I in $1..${NUM_DIVS}) {RU_div${I}_t2_2 })
+  );
+
+  any_mem_t2_2 
+  (
+      one_of($for (I in $1..${NUM_MEM_UNITS}) {RU_mem${I}_t2_2 })
+  );
+
+  any_branch_t2_2 
+  (
+      one_of($for (I in $1..${NUM_BRANCHES}) {RU_branch${I}_t2_2 })
+  );
+}
+
+/* Create the AND-OR trees that describes the how the processor resources
+ * are used as the operation executes.  This is the AND part of the
+ * AND/OR-tree representation for reservation tables.
+ *
+ * Any mixture of Table_Option, Resource_Unit, and Resource Usage entries
+ * may be specified in the 'use' field.
+ */
+SECTION Reservation_Table
+{
+  /* Simplifying assumption, ialu can execute all integer operations */
+  RL_IAlu       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_ialu_t2_2));
+  RL_Chk      (use(any_normal_slot_t0_0 any_decoder_t1_1 any_chk_t2_2));
+  RL_IMul       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_ialu_t2_2));
+  RL_INOP       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_ialu_t2_2));
+
+  /* Simplifying assumption, falu can execute all floating-point operations */
+  RL_FAlu       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_falu_t2_2));
+  RL_FMul       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_falu_t2_2));
+	
+  /* Divider is a seperate functional unit */ 	
+  RL_Div       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_div_t2_2));
+
+  /* Simplifying assumption, mem unit can execute all memory operations */
+  RL_Load       (use(any_normal_slot_t0_0 any_decoder_t1_1 any_mem_t2_2));
+  RL_Store      (use(any_normal_slot_t0_0 any_decoder_t1_1 any_mem_t2_2));
+
+  /* Branches use branch slots (set above based on branch placement rules) 
+   * but otherwise act like normal operations.
+   */
+  RL_Branch     (use(any_branch_slot_t0_0 any_decoder_t1_1 any_branch_t2_2));
+  RL_JSR        (use(any_branch_slot_t0_0 any_decoder_t1_1 any_branch_t2_2));
+}
+
+/* Declare all the times that operands (s0, d1, etc) can be read/written to.
+ * These are used to determine register flow dependence latencies.
+ * 
+ * "Sync" operands (ss0, sd0, etc.) are used to determine memory, control, 
+ * and synchronization flow dependence latencies.
+ */
+SECTION Operand_Latency
+{
+  /* Declare all the times source operands can be read.
+   * Time 0 (for latencies) is assumed to be just before the first
+   * execution stage (when most source operands are read).
+   */
+  $for (I in 0 1) 
+  {
+      s${I}       (time(${I}));
+      p${I}       (time(${I}));
+  }
+
+  /* Declare all the times destination operands can be written to.
+   * Given the above assumption, this should be set to the operation latency.
+   * (Since the flow-dependence distance with be (dest_lat - src_lat).
+   */
+  $def LATENCIES {1 2 3 15}
+  $for (I in ${LATENCIES}) 
+  {
+      d${I}       (time(${I}));
+  }
+
+  /* Declare all the times sync source operands can be read. */
+  $for (I in 0) 
+  {
+      ss${I}      (time(${I}));
+  }
+
+  /* Declare all the times sync dest operands can be written to. */
+  $for (I in 0) 
+  {
+      sd${I}      (time(${I}));
+  }
+}
+
+/* Declare all the operation latency combinations allowed.
+ * The flow-dependence distance between two operands are determined
+ * with (dest_lat - src_lat).  So if dest_lat = 2, and src_lat = 0,
+ * a flow dependence with a two-cycle latency will be added.
+ */
+SECTION Operation_Latency
+{
+  /* Simplifying assumption, assume all sources are read at time 0, and
+   * destinations are written at their latency.  Assume all flow dependences
+   * between dependent memory and branch operations are 0 cycles.
+   */  
+  $for (I in ${LATENCIES}) 
+  {
+      Lat${I}     (dest(d${I} d${I} d${I} d${I})
+                   src(s0 s0 s0 s0 s0 s0)
+                   pred(p0)
+                   mem_dest(sd0)
+                   ctrl_dest(sd0)
+                   sync_dest(sd0)
+                   mem_src(ss0)
+                   ctrl_src(ss0)
+                   sync_src(ss0));               
+  }
+
+  LatDP1	(dest(d1 d1 d1 d1)
+                 src(s0 s0 s0 s0 s0 s0)
+                 pred(p${PBDELAY})
+                 mem_dest(sd0)
+                 ctrl_dest(sd0)
+                 sync_dest(sd0)
+                 mem_src(ss0)
+                 ctrl_src(ss0)
+                 sync_src(ss0));	
+	
+  LatLd         (dest(d${LOAD_LAT} d${LOAD_LAT} d${LOAD_LAT} d${LOAD_LAT})
+                 src(s0 s0 s0 s0 s0 s0)
+                 pred(p0)
+                 mem_dest(sd0)
+                 ctrl_dest(sd0)
+                 sync_dest(sd0)
+                 mem_src(ss0)
+                 ctrl_src(ss0)
+                 sync_src(ss0));               
+}
+
+/* This section's entries group together an operation format, 
+ * reservation table,and an operation latency entry. 
+ * The requirements for all three entries need to be met in order for 
+ * the operation to be scheduled.
+ *
+ * Since we can model all the resource usage options with a single 
+ * AND/OR-tree-based reservation table and we have only one operation 
+ * format, we need only one scheduling alternative per operation type 
+ * to model resource constraints.
+ *
+ * However, if general speculation is enabled, create silent versions
+ * of operations that can except.
+ */
+SECTION Scheduling_Alternative
+{
+  ALT_IAlu     (format(A_AAAA_AAAAAA) resv (RL_IAlu) latency(Lat1));
+  ALT_IMul     (format(A_AAAA_AAAAAA) resv (RL_IAlu) latency(Lat2));
+  ALT_IDiv     (format(A_AAAA_AAAAAA) resv (RL_Div) latency(Lat15));
+  ALT_INOP     (format(A_AAAA_AAAAAA) resv (RL_IAlu) latency(Lat1));
+  ALT_CHECK    (format(A_AAAA_AAAAAA) resv (RL_Chk) latency(Lat1));
+  ALT_FAlu     (format(A_AAAA_AAAAAA) resv (RL_FAlu) latency(Lat3));
+  ALT_FMul     (format(A_AAAA_AAAAAA) resv (RL_FAlu) latency(Lat3));
+  ALT_FDiv     (format(A_AAAA_AAAAAA) resv (RL_Div) latency(Lat15));
+  ALT_Load     (format(A_AAAA_AAAAAA) resv (RL_Load) latency(LatLd));
+  ALT_Store    (format(A_AAAA_AAAAAA) resv (RL_Store) latency(Lat1));
+  ALT_Branch   (format(A_AAAA_AAAAAA) resv (RL_Branch) latency(LatDP1));
+  ALT_JSR      (format(A_AAAA_AAAAAA) resv (RL_JSR) latency(Lat1));
+
+  /* Create silent versions of operations if non-trapping operations
+   * are specified as being supported.
+   */
+  $if(${NON_TRAPPING_OPS} == 1) 
+  {
+    ALT_IDiv_S (format(A_AAAA_AAAAAA) resv (RL_Div) latency(Lat15) flags(SILENT));
+    ALT_FAlu_S (format(A_AAAA_AAAAAA) resv (RL_FAlu) latency(Lat3) flags(SILENT));
+    ALT_FMul_S (format(A_AAAA_AAAAAA) resv (RL_FAlu) latency(Lat3) flags(SILENT));
+    ALT_FDiv_S (format(A_AAAA_AAAAAA) resv (RL_Div) latency(Lat15) flags(SILENT));
+    ALT_Load_S (format(A_AAAA_AAAAAA) resv (RL_Load) latency(LatLd) flags(SILENT));
+  }
+}
+
+/* This section entries groups together all the scheduling alternatives
+ * for each operation type.  In this simplified machine description, it
+ * is used only to add silent (non-trapping) versions of operations.
+ */
+SECTION Operation
+{
+  OP_IAlu       (alt(ALT_IAlu));    
+  OP_IMul       (alt(ALT_IMul));     
+  OP_IDiv       (alt(ALT_IDiv));     
+  OP_INOP       (alt(ALT_INOP));
+  OP_CHECK      (alt(ALT_CHECK));     
+  OP_FAlu       (alt(ALT_FAlu));     
+  OP_FMul       (alt(ALT_FMul));    
+  OP_FDiv       (alt(ALT_FDiv));     
+  OP_Load       (alt(ALT_Load));    
+  OP_Store      (alt(ALT_Store));   
+  OP_Branch     (alt(ALT_Branch));   
+  OP_JSR        (alt(ALT_JSR));     
+
+  /* Add silent versions to above (excepting) alternative lists,
+   *  if non-trapping operations are specified as being supported.
+   */
+  $if(${NON_TRAPPING_OPS} == 1) 
+  {
+    OP_IDiv     (alt||(ALT_IDiv_S));     
+    OP_FMul     (alt||(ALT_FMul_S));    
+    OP_FAlu     (alt||(ALT_FAlu_S));     
+    OP_FDiv     (alt||(ALT_FDiv_S));     
+    OP_Load     (alt||(ALT_Load_S));    
+  }
+}
+
+
+/* This section maps Lcode operations to scheduling alternatives (thru
+ * Operation entries).  It also describes to the scheduler and register
+ * allocator some properties of the operation (which they use instead
+ * of Lcode library calls).  It is very important to get these flags correct,
+ * otherwise the operation will be treated incorrectly and illegal
+ * schedules might result (i.e., must mark loads, stores, branches, etc.
+ * properly).
+ */
+SECTION IMPACT_Operation
+{
+  /* Compiler directives, the IGNORE flag tells the scheduler to ignore
+   * them (not schedule them, draw dependences to them, etc.) and put them 
+   * at the top of the cb after scheduling.  Just use OP_INOP since 
+   * something is needed.)
+   */
+  $for (OPC in Lop_DEFINE Lop_ALLOC Lop_PROLOGUE Lop_SIM_DIR Lop_BOUNDARY)
+  {
+      ${OPC}      (op(OP_INOP) flags (IGNORE));
+  }
+
+  /* EPILOGUE is a special compiler directive that must go just before
+   * the RTS (i.e, cannot move to top), so mark as SYNC operation
+   * (nothing will be able to move past it).
+   */
+  Lop_EPILOGUE  (op(OP_INOP) flags(SYNC));
+
+  /* INTRINSIC is a special opcode representing add-on instructions
+   * that can be emulated with C function calls.
+   */
+  Lop_INTRINSIC  (op(OP_INOP));
+
+  /* Don't expect any no-ops, however better define */
+  Lop_NO_OP     (op(OP_INOP));
+
+  /* General check */
+  Lop_CHECK     (op(OP_CHECK) flags (CHK));
+
+  /* Jump subroutine opcodes, must be marked with JSR flag! */
+  $for (OPC in Lop_JSR Lop_JSR_FS)
+  {
+      ${OPC}      (op(OP_JSR) flags (JSR));
+  }
+
+  /* Return to subroutines opcodes, must be marked with RTS flag! */
+  $for (OPC in Lop_RTS Lop_RTS_FS)
+  {
+      ${OPC}      (op(OP_JSR) flags (RTS));
+  }
+
+  /* Unconditinal jump opcodes, must be marked with JMP flag! */
+  $for (OPC in Lop_JUMP Lop_JUMP_FS Lop_JUMP_RG Lop_JUMP_RG_FS)
+  {
+      ${OPC}      (op(OP_Branch) flags (JMP));
+  }
+
+  /* Conditional jump opcodes, must be marked with CBR flag!
+   * Assume branch unit can compare any type of operand.
+   */
+  $for (OPC in Lop_BR Lop_BR_F Lop_BEQ Lop_BEQ_FS Lop_BNE Lop_BNE_FS
+               Lop_BGT Lop_BGT_FS Lop_BGE Lop_BGE_FS
+               Lop_BLT Lop_BLT_FS Lop_BLE Lop_BLE_FS
+               Lop_BGT_U Lop_BGT_U_FS Lop_BGE_U Lop_BGE_U_FS
+               Lop_BLT_U Lop_BLT_U_FS Lop_BLE_U Lop_BLE_U_FS
+               Lop_BEQ_F Lop_BEQ_F_FS Lop_BNE_F Lop_BNE_F_FS
+               Lop_BGT_F Lop_BGT_F_FS Lop_BGE_F Lop_BGE_F_FS
+               Lop_BLT_F Lop_BLT_F_FS Lop_BLE_F Lop_BLE_F_FS
+               Lop_BEQ_F2 Lop_BEQ_F2_FS Lop_BNE_F2 Lop_BNE_F2_FS
+               Lop_BGT_F2 Lop_BGT_F2_FS Lop_BGE_F2 Lop_BGE_F2_FS
+               Lop_BLT_F2 Lop_BLT_F2_FS Lop_BLE_F2 Lop_BLE_F2_FS)
+  {
+      ${OPC}      (op(OP_Branch) flags (CBR));
+  }
+
+  /* Remap instruction
+   */
+  $for (OPC in Lop_REMAP)
+  {
+     ${OPC}      (op(OP_Branch));
+  }
+
+  /* Integer Ialu operations, no flags needed */
+  $for (OPC in Lop_MOV Lop_ABS Lop_OR Lop_AND 
+               Lop_XOR Lop_NOR Lop_NAND Lop_NXOR      
+               Lop_OR_NOT Lop_AND_NOT Lop_OR_COMPL Lop_AND_COMPL 
+               Lop_LSL Lop_LSR Lop_ASR Lop_ADD
+               Lop_ADD_SAT Lop_ADD_SAT_U
+               Lop_SUB_SAT Lop_SUB_SAT_U
+               Lop_SAT Lop_SAT_U
+               Lop_ADD_U Lop_SUB Lop_SUB_U Lop_RCMP Lop_EQ
+               Lop_NE Lop_GT Lop_GT_U Lop_GE Lop_GE_U 
+               Lop_LT Lop_LT_U Lop_LE Lop_LE_U
+	       Lop_EXTRACT_C Lop_EXTRACT_C2 Lop_EXTRACT Lop_EXTRACT_U Lop_DEPOSIT
+               Lop_SXT_C Lop_SXT_C2 Lop_SXT_I
+               Lop_ZXT_C Lop_ZXT_C2 Lop_ZXT_I
+               Lop_LSLADD)
+  {
+      ${OPC}      (op(OP_IAlu));
+  }
+
+  /* Integer multiple operations, no flags needed.
+   * Simplified, treat multiply_add ops, etc same as multiply.
+   */
+  $for (OPC in Lop_MUL Lop_MUL_U Lop_MUL_ADD Lop_MUL_ADD_U Lop_MUL_SAT Lop_MUL_SAT_U
+               Lop_L_MAC Lop_L_MSU Lop_MUL_SUB Lop_MUL_SUB_U Lop_MUL_SUB_REV 
+	       Lop_MUL_SUB_REV_U)
+  {
+      ${OPC}      (op(OP_IMul));
+  }
+
+  /* Integer divide operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_DIV Lop_DIV_U Lop_REM Lop_REM_U)
+  {
+      ${OPC}      (op(OP_IDiv) flags (EXCEPT));
+  }
+
+  /* Floating-point moves, cannot except */
+  Lop_MOV_F     (op(OP_FAlu));
+  Lop_MOV_F2    (op(OP_FAlu));
+
+  /* Floating-point alu operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_RCMP_F Lop_ABS_F Lop_ABS_F2 Lop_ADD_F Lop_ADD_F2
+               Lop_SUB_F Lop_SUB_F2 Lop_EQ_F Lop_EQ_F2
+               Lop_NE_F Lop_NE_F2 Lop_GT_F Lop_GT_F2
+               Lop_GE_F Lop_GE_F2 Lop_LT_F Lop_LT_F2
+               Lop_LE_F Lop_LE_F2 Lop_I_F Lop_F_I
+               Lop_I_F2 Lop_F2_I Lop_F_F2 Lop_F2_F)
+  {
+      ${OPC}      (op(OP_FAlu) flags (EXCEPT));
+  }
+
+  /* Floating-point multiple operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   * Simplified, treat multiply_add ops, etc same as multiply.
+   */
+  $for (OPC in Lop_MUL_F Lop_MUL_F2 Lop_MUL_ADD_F Lop_MUL_ADD_F2
+               Lop_MUL_SUB_F Lop_MUL_SUB_REV_F 
+               Lop_MUL_SUB_F2 Lop_MUL_SUB_REV_F2)
+  {
+      ${OPC}      (op(OP_FMul) flags (EXCEPT));
+  }
+
+  /* Floating-point divide operations.  EXCEPT flag must be specified.
+   * Will not speculate above branch unless one of the scheduling
+   * alternatives is a SILENT version.
+   * Simplified, treat sqrt ops, etc same as divide.
+   */
+  $for (OPC in Lop_DIV_F Lop_DIV_F2 Lop_SQRT_F Lop_SQRT_F2)
+  {
+      ${OPC}      (op(OP_FDiv) flags (EXCEPT));
+  }
+
+  /* Loop over the possible data types for memory operations */
+  $for (TYPE in C C2 I Q F F2)
+  {
+    /* Load memory opcodes, must be marked with EXCEPT LOAD flag! 
+     * Will not speculate above branch unless one of the scheduling
+     * alternatives is a SILENT version.
+     * Pre and post increment loads (LD_PRE, LD_POST) are not currently 
+     * supported (as of IMPACT release 2.32).
+     */
+     Lop_LD_${TYPE} (op(OP_Load) flags (EXCEPT LOAD));
+
+
+    /* Store memory opcodes, must be marked with EXCEPT STORE flag! 
+     * Pre and post increment stores (ST_PRE, ST_POST) are not currently 
+     * supported (as of IMPACT release 2.32).
+     */
+     Lop_ST_${TYPE} (op(OP_Store) flags (EXCEPT STORE));
+  }
+
+  /* Unsigned character/short loads (there are no unsigned stores) */
+  Lop_LD_UC       (op(OP_Load) flags (EXCEPT LOAD));
+  Lop_LD_UC2      (op(OP_Load) flags (EXCEPT LOAD));
+  Lop_LD_UI       (op(OP_Load) flags (EXCEPT LOAD));
+
+  /* Predicate load/store operations */
+  Lop_PRED_LD     (op(OP_Load) flags(EXCEPT LOAD));
+  Lop_PRED_ST     (op(OP_Store) flags(EXCEPT STORE));
+
+  /* Load/store block of 32 predicate registers (used by register allocator) */
+  Lop_PRED_LD_BLK (op(OP_Load) flags(NOSPEC EXCEPT LOAD));
+  Lop_PRED_ST_BLK (op(OP_Store) flags(NOSPEC EXCEPT STORE));
+
+  /* PRED_CLEAR and PRED_SET clears/sets a single predicate, primarily for 
+   * the convenence of the compiler writer. They need to be folded into
+   * later predicate definitions (via optimizations) and the rest converted 
+   * into operations that set/clear multiple predicates (perhaps up to 32) 
+   * in a single operation.  Since these pred clear/set optimizations are
+   * not currently supported (as of IMPACT release 2.32), make an aggressive 
+   * assumption that they are free and ignore their cost by treating them 
+   * as compiler directives.  (The alternative, to treat them as regular 
+   * operations is way too conservative, since many of them can be folded 
+   * in with later predicate definitions (thus eliminated) and the rest
+   * can be converted into at least predicate definitions (which allow
+   * setting two predicates per operation).
+   */
+  Lop_PRED_CLEAR(op(OP_IAlu) flags(IGNORE));
+  Lop_PRED_SET  (op(OP_IAlu) flags(IGNORE));
+
+  /* Predicate definition opcodes using integer comparisons.
+   * No flags needed. 
+   */
+  $for (OPC in Lop_CMP Lop_PRED_EQ Lop_PRED_NE Lop_PRED_GT Lop_PRED_GT_U 
+               Lop_PRED_GE Lop_PRED_GE_U Lop_PRED_LT Lop_PRED_LT_U
+               Lop_PRED_LE Lop_PRED_LE_U)
+  {
+      ${OPC}      (op(OP_IAlu));
+  }
+
+  /* Predicate definition opcodes using floating-point comparisons.
+   * EXCEPT flag must be specified. Will not speculate above branch
+   * unless one of the scheduling alternatives is a SILENT version.
+   */
+  $for (OPC in Lop_CMP_F Lop_PRED_EQ_F2 Lop_PRED_NE_F2 Lop_PRED_GT_F2 Lop_PRED_GE_F2
+               Lop_PRED_LT_F2 Lop_PRED_LE_F2 Lop_PRED_EQ_F Lop_PRED_NE_F
+               Lop_PRED_GT_F Lop_PRED_GE_F Lop_PRED_LT_F Lop_PRED_LE_F)
+  {
+      ${OPC}      (op(OP_FAlu) flags (EXCEPT));
+  }
+}
+
+
+
diff -urN openimpact-1.0rc4/mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2 openimpact-1.0rc4.Limpact/mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2
--- openimpact-1.0rc4/mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2	1969-12-31 18:00:00.000000000 -0600
+++ openimpact-1.0rc4.Limpact/mdes/Limpact/PACT_SIMPLE_TEMPLATE.hmdes2	2004-09-17 14:41:04.000000000 -0500
@@ -0,0 +1,90 @@
+/*****************************************************************************\
+ *
+ *		      Illinois Open Source License
+ *                     University of Illinois/NCSA
+ *                         Open Source License
+ *
+ * Copyright (c) 2004, The University of Illinois at Urbana-Champaign.
+ * All rights reserved.
+ *
+ * Developed by:             
+ *
+ *		IMPACT Research Group
+ *
+ *		University of Illinois at Urbana-Champaign
+ *
+ *              http://www.crhc.uiuc.edu/IMPACT
+ *              http://www.gelato.org
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal with the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimers.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimers in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the names of the IMPACT Research Group, the University of
+ * Illinois, nor the names of its contributors may be used to endorse
+ * or promote products derived from this Software without specific
+ * prior written permission.  THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
+ * LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+ * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS WITH THE SOFTWARE.
+ *
+\*****************************************************************************/
+/*****************************************************************************\
+ *
+ *  File:  IMPACT_SIMPLE_TEMPLATE.hmdes2
+ *
+ *  Description:  Simple machine description template for wide-variety of 
+ *                experimental processors that execute IMPACT's Lcode.
+ *                This simplified template does not model register ports and
+ *                uses a fairly simple function unit model.  It is designed
+ *                to be relatively easy to understand and modify.  
+ * 
+ *  Note: For hmdes2 documentation (slightly out-of-date), see:
+ * 
+ *          HMDES Version 2 Specification 
+ *          John C. Gyllenhaal, Wen-mei W. Hwu and B. Ramakrishna Rau
+ *          IMPACT Technical report, IMPACT-96-03, 
+ *          University of Illinois, Urbana IL. 1996.
+ *          http://www.crhc.uiuc.edu/IMPACT/ftp/report/impact-96-03.hmdes2.pdf
+ *
+ *  Note: Although IMPACT's and HPL's (Elcor) machine descriptions share a 
+ *        common host language "MD" (aka as "dabble" at HPL), they are not 
+ *        currently compatible with each other.  This machine description 
+ *        cannot be used with Trimaran's Elcor-based scheduler and Elcor's
+ *        machine descriptions cannot be used with IMPACT-based schedulers.
+ *        
+ *  Creation Date :  June 1999
+ *
+ *  Author:  John C. Gyllenhaal, Wen-mei Hwu
+ *
+ *  Revisions:
+ *
+\*****************************************************************************/
+
+/* 
+ * Processor resource configuration parameters. 
+ */
+
+$def WIDTH              8
+$def NUM_IALUS          ${WIDTH}
+$def NUM_FALUS          ${WIDTH}
+$def NUM_MEM_UNITS      ${WIDTH}
+$def NUM_BRANCHES       ${WIDTH}
+
+$include "${IMPACT_REL_PATH}/mdes/Limpact/PACT_BASE_TEMPLATE.hmdes2"
diff -urN openimpact-1.0rc4/mdes/Makefile.am openimpact-1.0rc4.Limpact/mdes/Makefile.am
--- openimpact-1.0rc4/mdes/Makefile.am	2007-02-07 15:16:32.319821000 -0600
+++ openimpact-1.0rc4.Limpact/mdes/Makefile.am	2007-02-07 15:17:19.223170000 -0600
@@ -3,7 +3,7 @@
 ## files need to be specified relative to the top level directory.
 
 include $(srcdir)/mdes/structure/Makefile.am
-
+include $(srcdir)/mdes/Limpact/Makefile.am
 include $(srcdir)/mdes/Ltahoe/Makefile.am
 
 
@@ -16,9 +16,9 @@
 
 ## A target to support cleaning everything under this subdirectory.
 mdes/clean:
-	mdes/structure/clean  mdes/Ltahoe/clean 
+	mdes/structure/clean mdes/Limpact/clean mdes/Ltahoe/clean 
 	
 
 mdes_CLN = \
-	$(mdes_structure_CLN)  $(mdes_Ltahoe_CLN) 
+	$(mdes_structure_CLN) $(mdes_Limpact_CLN) $(mdes_Ltahoe_CLN)